x86
Instruction Set Architecture

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Vector AES Instructions (VAES) is an x86 extension.

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Overview

VAESDEC

...

VAESDECLAST

...

VAESENC

...

VAESENCLAST

...

Detection

The VAES feature flag indicates support for the AVX variant of these instructions operating on 256-bit vectors.

The AVX-512 variant with EVEX encoding operating on 512-bit vectors are supported if the VAES and AVX512F (Foundation) flags are set. The 128- and 256-bit versions with EVEX encoding are supported if the AVX512VL (Vector Length) flag is set as well.

The earlier AES extension provides SSE and AVX variants of these instructions operating on 128-bit vectors.

CPUID		Instruction Set
Input	Output
EAX=07H, ECX=0	ECX[bit 09]	VAES
EAX=07H, ECX=0	EBX[bit 16]	AVX512F
EAX=07H, ECX=0	EBX[bit 31]	AVX512VL

Microarchitecture support

Designer	Microarchitecture	Year	Support Level
			VAES AVX	VAES AVX-512 (128/256)	VAES AVX-512 (512)
AMD	Zen 3	2020	✔	✘	✘
	Zen 4	2022	✔	✔	✔

Intrinsic functions

// VAESDEC
__m256i _mm256_aesdec_epi128(__m256i, __m256i);
__m512i _mm512_aesdec_epi128(__m512i, __m512i);
// VAESDECLAST
__m256i _mm256_aesdeclast_epi128(__m256i, __m256i);
__m512i _mm512_aesdeclast_epi128(__m512i, __m512i);
// VAESENC
__m256i _mm256_aesenc_epi128(__m256i, __m256i);
__m512i _mm512_aesenc_epi128(__m512i, __m512i);
// VAESENCLAST
__m256i _mm256_aesenclast_epi128(__m256i, __m256i);
__m512i _mm512_aesenclast_epi128(__m512i, __m512i);