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Kirin 980
General Info
Designer	HiSilicon, ARM Holdings
Manufacturer	TSMC
Model Number	980
Market	Mobile
Introduction	August 31, 2018 (announced) August 31, 2018 (launched)
General Specs
Family	Kirin
Frequency	2,600 MHz, 1,920 MHz, 1,800 MHz
Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Cortex-A76, Cortex-A55
Core Name	Cortex-A76, Cortex-A55
Process	7 nm
Transistors	6,900,000,000
Technology	CMOS
Die	74.13mm²
Word Size	64 bit
Cores	8
Threads	8

Kirin 980 is a 64-bit high-performance mobile ARM LTE SoC designed by HiSilicon and introduced in late 2018. Fabricated on TSMC's 7 nm process, the 980 incorporates four big Cortex-A76 cores operating at up to 2.6 GHz along with four little Cortex-A55 cores operating at up to 1.8 GHz. This SoC has an LTE modem supporting 1.4 Gbps download (Cat21), incorporates an ARM Mali-G76, and supports LPDDR4X-4266 memory.

Cache

Main articles: Cortex-A55 § Cache and Cortex-A76 § Cache

For the Cortex-A76:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 512 KiB 524,288 B 0.5 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 4x64 KiB     L1D$ 256 KiB 262,144 B 0.25 MiB 4x64 KiB     L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     4x512 KiB

For the Cortex-A55:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB     L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB     L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     4x128 KiB

Memory controller

The Kirin 980 supports 4-channel LPDDR4X up to 2133 MHz. Each channel supports at most two ranks.

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4X-4266 Supports ECC No Max Mem 8 GiB Controllers 1 Channels 4 Width 16 bit Max Bandwidth 31.78 GiB/s 32,542.72 MiB/s 34.124 GB/s 34,123.515 MB/s 0.031 TiB/s 0.0341 TB/s Bandwidth Double 15.89 GiB/s Quad 31.78 GiB/s

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU Mali-G76 Designer ARM Holdings Execution Units 10 Max Displays 2 Frequency 720 MHz 0.72 GHz 720,000 KHz Output DSI Standards DirectX 12 OpenCL 1.2 OpenGL ES 3.2 OpenVG 1.1 Vulkan 1.0

Wireless

• LTE Modem
  • DL: Up to User Equipment (UE) category 21
    • Downlink of up to 1.4 Gbps (4x4 MIMO + 256QAM 3CC CA = 1.2 Gbps, 2x2 MIMO + 256QAM + 1CC = 200 Mbps)
  • UL: Up to User Equipment (UE) category 18
    • Uplink of up to 200 Mbps (2x2 MIMO, 256-QAM, 1x20MHz CA)
• Wi-Fi 802.11 ac
• Bluetooth 5
• NFC
• GPS / A-GPS / GLONASS / BDS

Utilizing devices

• Huawei P30
• Huawei P30 Pro
• Huawei Mate 20
• Huawei Mate 20 Pro
• Huawei Mate 20 X
• Huawei Mate 20 X 5G
• Huawei Mate 20 RS Porsche Design
• Huawei Nova 5T
• Honor Magic 2
• Honor View 20 / V20
• Huawei Mate X
• Huawei Honor 20
• Huawei Honor 20 Pro
• Huawei Mediapad M6 8.4
• Huawei Mediapad M6 10.8
• Huawei Nova 5 Pro

Bibliography

• Huawei Kirin 980 Keynote, 2018 IFA