• intel/cores/kaby lake g
  |image=kaby lake g (front).png ...chitecture and incorporate a discrete [[AMD]] {{amd|Vega|l=arch}} graphics processor. These chips are targeted towards ultimate mobile gaming experience. Kaby L
  5 KB (728 words) - 18:07, 12 July 2018
• intel/xeon e
  | image = | no image = Yes
  11 KB (1,554 words) - 11:14, 2 June 2019
• intel/cores/coffee lake r
  |no image=Yes All Coffee Lake R processors have the following:
  4 KB (523 words) - 01:38, 7 May 2019
• intel/cores/skylake de
  |image=skylake-de (front).png '''Skylake DE''' ('''SKL-DE''') is the processor core for [[Intel]]'s single-chip high-performance low-power dense processor
  6 KB (774 words) - 01:49, 25 February 2019
• amd/ryzen embedded
  | image = File:ryzen embedded logo.png ...}} integrated graphics processor in {{amd|FP5|package FP5|l=package}}. All models have the following features in common.
  11 KB (1,642 words) - 03:53, 2 January 2021
• amd/cores/renoir
  |no image=Yes All Renoir processors have the following:
  5 KB (681 words) - 14:07, 17 March 2023
• movidius/myriad
  | image = File:myriad 3D logo.png | no image =
  3 KB (320 words) - 22:43, 12 March 2018
• movidius/microarchitectures/shave v2.0
  ...for expensive physics acceleration in smartphones has forced a re-focus on image and vision processing. Their architecture was versatile enough that it allo ...ly benefits most code. The chip features an [[L2 cache]] that is shared by all the cores as well as an integrated [[DDR2]] [[integrated memory controller|
  12 KB (1,749 words) - 19:05, 20 January 2021
• intel/cores/cascade lake sp
  |image=cascade lake sp (front).png ...{{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}} [[processor families]].
  9 KB (1,291 words) - 13:48, 27 February 2020
• cavium/thunderx2
  | image = ThunderX2 logo.png ...r own {{cavium|thunderx2|second-generation|l=arch}} microarchitecture with models up to 54 cores. Cavium focused the {{\\|ThunderX}} design on the networking
  4 KB (494 words) - 20:33, 26 April 2019
• intel/cores/amber lake y
  |no image=Yes |image=kaby lake y (front).png
  4 KB (538 words) - 09:43, 27 July 2020
• intel/cores/ice lake y
  |image=File:ice lake y (front).png |back image=File:ice lake y (back).png
  5 KB (731 words) - 19:08, 26 February 2020
• intel/cores/whiskey lake u
  |no image=No ...n-Package Interconnect (OPI) interface, allowing for 4 GT/s transfer rate. All Whiskey Lake U processors use {{intel|FCBGA-1528}} packages.
  4 KB (508 words) - 23:23, 2 August 2020
• intel/cores/ice lake u
  |image=ice lake u (front).png |back image=File:ice lake u (back).png
  6 KB (810 words) - 23:19, 12 May 2020
• intel/cores/comet lake s
  |no image=Yes All Comet Lake S processors have the following:
  2 KB (347 words) - 17:57, 21 October 2019
• intel/cores/comet lake u
  |no image=No All Comet Lake U processors have the following:
  4 KB (529 words) - 23:19, 12 May 2020
• intel/cores/coffee lake e
  |image=coffee lake e (front).png |image 2=coffee lake e (back).png
  5 KB (748 words) - 12:14, 2 June 2019
• hisilicon/kunpeng
  | image = hi1616 (front).png == Models ==
  5 KB (656 words) - 05:07, 13 October 2019
• amd/cores/castle peak
  |no image=Yes ...Gen 1, 2, 3 (6 Gb/s) link. Up to 32 SATA ports are available from the processor in total, as well as four USB 3.2 Gen [[wikipedia:USB 3.0#USB 3.2|2×1]] (1
  7 KB (1,002 words) - 14:16, 17 March 2023
• amd/packages/socket tr4
  The following AMD processor families use Socket TR4: |rowspan="2"|{{amd|CPUID#Family 23 (17h)|Family 17h}} Models 00h–0Fh
  86 KB (17,313 words) - 02:48, 13 March 2023

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