• 750 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  1 KB (134 words) - 06:17, 20 July 2018
• 280 nm lithography process
  ...m process was a standard CMOS process. Featuring a smaller transistor gate pitch, the process shared similar metal layer sizes to the [[0.35 µm]] (this is |Contacted Gate Pitch
  2 KB (225 words) - 06:11, 20 July 2018
• 220 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  975 bytes (117 words) - 06:10, 20 July 2018
• 240 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  820 bytes (102 words) - 06:10, 20 July 2018
• 80 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  1 KB (136 words) - 05:55, 20 July 2018
• 700 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  928 bytes (114 words) - 06:17, 20 July 2018
• intel/microarchitectures/coffee lake
  ...nsistor geometry, the "14nm++" actually uses a more relaxed contacted poly pitch of 84 nm (from previously 70nm). There is no real density change despite th | Gate Pitch || 70 nm || 84 nm || 1.20x
  30 KB (4,192 words) - 13:48, 10 December 2023
• 3 nm lithography process
  | process 1 fin pitch =   | process 1 fin pitch Δ =  
  5 KB (558 words) - 19:04, 29 December 2023
• mtr-mm²
  ...iance in SRAM-to-logic ratio between popular chips. Furthermore, the metal pitch does not play a role in limiting SRAM as it does with other standard cells. ...has a poly pitch of 54 nm and cells on Intel's 10 nm use a single [[dummy gate]]. For 0.6 NAND2 + 0.4 SFF, Intel's 10nm has a density of 100.76 MTr/mm² a
  4 KB (634 words) - 12:16, 25 April 2020
• nodelet
  ...n]] or improve the device performance through the relaxation of the [[gate pitch]]. An example of recent nodelets include [[12 nm]], [[11 nm]], and [[8 nm]]
  970 bytes (135 words) - 20:10, 19 July 2018
• self-aligned contact
  ...d]] loss due to misalignment and partial overlaps of the contacts over the gate. ...a need to be able to length much closer to the gate and even on top of the gate. In addition to the lack of space, problems with landing the contacts are e
  4 KB (575 words) - 11:12, 13 October 2019
• scaling booster
  ...ocess nodes]] continues to shrink, classical scaling vectors (e.g., [[gate pitch]]) becomes increasingly challenging. There are multiple reasons for this in ...proving the yield by preventing yield loss due to the contact shorting the gate.
  4 KB (600 words) - 00:24, 21 June 2022
• single diffusion break
  ...or process flow technique that eliminates the need for an additional dummy gate padding at the cell boundaries. SDB is [[scaling booster|used to enable agg ...[poly gate]] [[gate length|length]]. In practice, there is no actual dummy gate. Instead, just the trench isolation remains.
  2 KB (294 words) - 18:24, 25 June 2022

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