• intel/xeon platinum/9222
  '''Xeon Platinum 9222''' is a [[32-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 92 ...not be purchased independently and is only sold as part of Intel's S9200WK Compute Module.
  3 KB (530 words) - 20:42, 3 April 2019
• intel/xeon platinum/9221
  '''Xeon Platinum 9221''' is a [[32-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 92 ...not be purchased independently and is only sold as part of Intel's S9200WK Compute Module.
  3 KB (530 words) - 02:16, 4 June 2019
• nervana/nnp
  ...and [[OCP OAM|OAM]] form factors that have high TDPs designed for maximum performance at the data center and for workstations. Unlike the NNP-T, NNP-I inference ...ormance uplift. Intel claims that these chips have about 3-4x the training performance of first generation. All NNP-T 1000 chips come with 32 GiB of four [[HBM2]]
  8 KB (1,145 words) - 12:42, 1 February 2020
• hisilicon/microarchitectures/taishan v110
  '''TaiShan v110''' is the successor to the {{\\|TaiShan v100}}, a high-performance [[ARM]] server microarchitecture designed by [[HiSilicon]] for [[Huawei]]'s ...ormance [[ARM]] core and SoC design. The chip, which incorporates multiple compute dies and an I/O is a multi-chip package, is fabricated on [[TSMC]]'s [[7 nm
  7 KB (947 words) - 10:20, 9 September 2022
• intel/microarchitectures/lakefield
  '''Lakefield''' ('''LKF''') is a high-performance low-power [[3d integrated circuit|3D]] microarchitecture designed by Intel ** [[10 nm]] compute field
  5 KB (769 words) - 06:44, 14 August 2021
• amd/epyc/7232p
  ...Milam; Subramony, Mahesh (2020). <i>2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products</i>. 2020 IEEE International Solid-State Circui
  5 KB (810 words) - 02:29, 19 August 2022
• amd/epyc/7252
  ...ased on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates two compute dies fabricated on a [[TSMC]] [[7 nm process]] and an I/O die fabricated on ...Milam; Subramony, Mahesh (2020). <i>2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products</i>. 2020 IEEE International Solid-State Circui
  5 KB (733 words) - 19:48, 9 January 2021
• amd/epyc/7272
  ...ased on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates two compute dies fabricated on a [[TSMC]] [[7 nm process]] and an I/O die fabricated on ...Milam; Subramony, Mahesh (2020). <i>2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products</i>. 2020 IEEE International Solid-State Circui
  5 KB (728 words) - 19:35, 9 January 2021
• amd/epyc/7282
  ...ased on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates two compute dies fabricated on a [[TSMC]] [[7 nm process]] and an I/O die fabricated on ...Milam; Subramony, Mahesh (2020). <i>2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products</i>. 2020 IEEE International Solid-State Circui
  5 KB (733 words) - 19:37, 12 January 2021
• intel/microarchitectures/spring hill
  ** 12 inference and compute units (ICEs) *** DL compute grid
  9 KB (1,292 words) - 08:41, 26 March 2020
• supercomputers/archer
  <tr><th>Peak Performance</th><td>2.551 [[petaFLOPS]] (DP)</td></tr> ...erlink all the nodes. ARCHER uses a [[Dragonfly topology]]. There are four compute nodes connected per each Aries router, 188 nodes per cabinet, and two cabin
  3 KB (330 words) - 14:51, 21 October 2019
• supercomputers/archer 2
  ...e planned successor to {{\\|ARCHER}} intended to deliver an average of 11x performance improvement over its predecessor. The system is based on [[Cray]] Shasta an <tr><th>Peak Performance</th><td>26.35 petaFLOPS</td></tr>
  1 KB (200 words) - 01:15, 21 October 2019
• supercomputers/hector
  ...oyed in a number of phases with each phase upgrading it to over double the performance. ! Cores || Peak Compute
  8 KB (1,037 words) - 14:44, 21 October 2019
• samsung/exynos/990
  '''Exynos 990''' is a {{arch|64}} [[octa-core]] [[ARM]] high performance mobile [[system on a chip]] designed by [[Samsung]] and introduced in [[202 ...new NPU features two execution cores. The new NPU is capable of a peaking compute of fifteen trillion operations per second (TOPs).
  4 KB (635 words) - 00:28, 8 November 2023
• centaur/microarchitectures/cha
  ...rket. Fabricated on TSMC [[16 nm process]], the chip integrates eight high-performance [[x86]] "CNS" cores along with a brand new clean-sheet design "NCORE" [[neu ...ores also introduce the {{x86|AVX-512}} extension in order to offer better performance, flexibility, and offer better ISA compatibility with other [[x86]] vendors
  24 KB (3,792 words) - 04:37, 30 September 2022
• nervana/nnp/nnp-i 1300
  ...pring Hill#Inference Compute Engine (ICE)|ICEs|l=arch}} enabled for a peak performance of 170 [[TOPS]] at a TDP of 75 W. == Peak Performance ==
  2 KB (220 words) - 12:49, 1 February 2020
• nervana/nnp/nnp-i 1100
  ...{intel|Spring Hill#Inference Compute Engine (ICE)|ICEs|l=arch}} for a peak performance of 50 [[TOPS]] at a TDP of 12 W. This chip comes in an [[M.2]] [[accelerato == Peak Performance ==
  2 KB (227 words) - 12:48, 1 February 2020
• arm holdings/microarchitectures/mlp
  ==== Compute Engine ==== :[[File:mlp compute engine block diagram.svg|550px]]
  9 KB (1,379 words) - 22:35, 6 February 2020
• arm holdings/ethos
  ...e through various configurations based on the SRAM sizes and the number of compute engines. ...rm's {{armh|CCN-500}} or {{armh|CMN-600}} interconnects to scale to higher performance. For example, eight of the {{armh|Ethos-N77|l=core}} can be integrated toge
  4 KB (557 words) - 23:45, 10 February 2020
• amd/List of AMD publications
  ...:File:AMD-K5 Processor Performance Brief (June, 1996).pdf|AMD-K5 Processor Performance Brief]]||1996-06|| ...7.pdf White Paper: Next Generation Connectivity Solutions: AMD’s Managed Performance Portfolio]||1998-03||
  181 KB (24,861 words) - 16:02, 17 April 2022

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