• exponential technology/x704/533
  | max cpus = 1 | max memory =
  3 KB (337 words) - 16:13, 13 December 2017
• exponential technology/x704/500
  | max cpus = 1 | max memory =
  3 KB (331 words) - 16:13, 13 December 2017
• exponential technology/x704/466
  | max cpus = 1 | max memory =
  3 KB (331 words) - 16:13, 13 December 2017
• princeton/piton
  | max cpus = 20,000 | max memory =
  6 KB (731 words) - 15:41, 5 July 2018
• amd/microarchitectures/k6
  ** 16-entry return address stack ...h><th>Core</th><th>Launched</th><th>Power Dissipation</th><th>Freq</th><th>Max Mem</th></tr>
  4 KB (578 words) - 18:57, 22 May 2019
• amd/microarchitectures/zen
  === Memory Hierarchy === ...n all four areas of the core (the front end, the execution engine, and the memory subsystem) as well as Zen's new [[SoC]] CCX (CPU Complex) modular design. T
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  ** Memory subsystem * <code>{{x86|MCOMMIT}}</code> - Commit stores to memory
  57 KB (8,701 words) - 22:11, 9 October 2022
• pezy/pezy-scx/pezy-sc2
  ...performance further, the MIPS cores and the PEZY cores now share the same address space, reducing data transfer overhead. It's worth noting that the use of p ...onally, there is another 40 MiB consisting of 20 KiB per PE of scratch pad memory. This was increased from 16 KiB in the {{\\|Pezy-SC}}.
  5 KB (683 words) - 11:15, 22 September 2018
• pezy/pezy-scx/pezy-scnp
  .... The new chip, which made use of a slightly different package in order to address a number of signal-related issues (DRAM/PCIe signal failures). The new mode Additionally, there is another 16 MiB of scratch-pad memory consisting of 16 KiB per PE.
  3 KB (403 words) - 11:15, 22 September 2018
• intel/microarchitectures/gen9.5
  ...nario demands it (such as in cases where higher fixed-function geometry or memory demands occur). ...down the pipeline. In addition, the CS unit reads “constant data” from memory
  29 KB (3,752 words) - 13:14, 19 April 2023
• intel/microarchitectures/gen9
  ** Shared Virtual Memory (SVM) improvements ** Floating point atomics (min/max/cmpexch)
  33 KB (4,255 words) - 17:41, 1 November 2018
• ibm/microarchitectures/power9
  |stages max=16 ! SoC Codename || SoC Description || Module || Memory Channels || PCIe || {{ibm|XBUS}} || [[OpenCAPI]]
  14 KB (1,905 words) - 23:38, 22 May 2020
• qualcomm/microarchitectures/falkor
  |stages max=15 === Memory Hierarchy ===
  6 KB (822 words) - 13:01, 19 May 2021
• acorn/microarchitectures/arm1
  * {{arm|26-bit|26-bit address space}} ...simplify system design, these clocks may be stretched to work in-sync with memory access times.
  12 KB (1,886 words) - 12:56, 14 January 2021
• intel/microarchitectures/merced
  | stages max = ** Early zero bubble predictor using Target Address Registers controlled by the compiler
  7 KB (978 words) - 21:16, 20 January 2021
• marvell/armada/610
  | max cpus = 1 | max memory = 2 GiB
  6 KB (683 words) - 16:31, 13 December 2017
• marvell/armada/618
  | max cpus = 1 | max memory = 2 GiB
  6 KB (666 words) - 16:31, 13 December 2017
• marvell/armada/628
  | max cpus = 1 | max memory =
  6 KB (681 words) - 17:03, 24 January 2018
• dec/microarchitectures/alpha 21064
  |stages max=12 ** Separate data & address buses
  4 KB (527 words) - 02:09, 4 August 2017
• acorn/microarchitectures/arm2
  ...ements. The ARM2 was capable of exceeding 10 MIPS when not bottlenecked by memory with an average of around 6 MIPS. Unlike the ARM1 which was predominantly a * > 2x MIPS when not bottlenecked by memory
  14 KB (2,093 words) - 04:42, 10 July 2018

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