From WikiChip
File list
This special page shows all uploaded files.
First page |
Previous page |
Next page |
Last page |
Date | Name | Thumbnail | Size | Description | Versions |
---|---|---|---|---|---|
10:20, 4 June 2018 | vulcan block diagram.svg (file) | ![]() |
93 KB | 8 | |
22:44, 3 June 2018 | ThunderX2 logo.png (file) | ![]() |
63 KB | Cavium {{cavium|ThunderX2}} logo. | 1 |
21:02, 3 June 2018 | cavium vulcan die core cluster (annotated).png (file) | ![]() |
59 KB | {{cavium|Vulcan|l=arch}} die core cluster. Annotated by WikiChip. | 1 |
21:02, 3 June 2018 | cavium vulcan die core cluster.png (file) | ![]() |
51 KB | {{cavium|Vulcan|l=arch}} die core cluster. | 1 |
11:31, 1 June 2018 | vulcan chip block diagram.svg (file) | ![]() |
90 KB | slight adjustment | 3 |
11:19, 1 June 2018 | vulcan overview-2way.svg (file) | ![]() |
90 KB | {{cavium|Vulcan|l=arch}} 2-way overview. Image by WikiChip. | 1 |
22:17, 26 May 2018 | cambricon mlu100 card.png (file) | ![]() |
132 KB | Cambricon Cambricon MLU100 accelerator card. Image by Cambricon. | 1 |
21:59, 26 May 2018 | cambricon mlu100 front.png (file) | ![]() |
150 KB | 2 | |
18:24, 25 May 2018 | google pvc floorplan.png (file) | ![]() |
766 KB | Google's {{google|Pixel Visual Core|PVC}} floorplan. Image by google. | 1 |
18:24, 25 May 2018 | google pvc die.png (file) | ![]() |
1.16 MB | Google's {{google|Pixel Visual Core|PVC}} die shot. Image by google. | 1 |
22:05, 24 May 2018 | sdm710-mobile-platform-presentation.pdf (file) | ![]() |
5.16 MB | SDM710 presentation. | 1 |
22:05, 24 May 2018 | sdm710-brief.pdf (file) | ![]() |
1.11 MB | SDM710 brief. | 1 |
21:24, 24 May 2018 | snapdragon 710 (back).png (file) | ![]() |
1.41 MB | Snapdragon 710, back. Image by Qualcomm. | 1 |
21:24, 24 May 2018 | snapdragon 710 (front).png (file) | ![]() |
1.28 MB | Snapdragon 710, front. Image by Qualcomm. | 1 |
10:20, 23 May 2018 | scan flip flop.svg (file) | ![]() |
9 KB | scan flip-flop. | 1 |
10:20, 23 May 2018 | chain scan flip flop.svg (file) | ![]() |
28 KB | scan chain using a scan flip-flop. | 1 |
08:58, 16 May 2018 | cannon lake soc block diagram (dual).svg (file) | ![]() |
25 KB | WikiChip's drawing of {{intel|Cannon Lake|l=arch}} SOC in a block diagram. Dual core SoC. | 1 |
17:58, 11 May 2018 | intel-ref-248966-040.pdf (file) | ![]() |
6.5 MB | Intel IA-32 Architecture Optimization Reference Manual 248966, Revision 40. See {{intel|Documents}}. | 1 |
22:40, 7 May 2018 | nvidia nvswitch die shot.png (file) | ![]() |
1.3 MB | Nvidia's {{nvidia|NVSwitch}} die shot. Image by Nvidia. * Annotated: File:nvidia_nvswitch_die_shot_(annotated).png | 1 |
22:40, 7 May 2018 | nvidia nvswitch die shot (annotated).png (file) | ![]() |
1.15 MB | Nvidia's {{nvidia|NVSwitch}} die shot. Image by Nvidia. Annotated by WikiChip. * Original: File:nvidia_nvswitch_die_shot_(annotated).png | 1 |
22:11, 7 May 2018 | dgx2 nvswitch baseboard diagram with two boards connected.svg (file) | ![]() |
277 KB | WikiChip diagram of the {{nvidia|DGX-2}} with two baseboards fully connected. Each baseboard is fully connecting 8 {{nvidia|V100}} GPUs using six {{nvidia|NVSwitches}}. | 1 |
21:49, 7 May 2018 | dgx2 nvswitch baseboard diagram.svg (file) | ![]() |
149 KB | WikiChip diagram of the {{nvidia|DGX-2}} baseboard fully connecting 8 {{nvidia|V100}} GPUs using six {{nvidia|NVSwitches}}. | 1 |
12:15, 5 May 2018 | lake crest pcie card internal.png (file) | ![]() |
1.58 MB | Intel Nervana {{nervana|Lake Crest|l=arch}}. Image by Intel. | 1 |
03:21, 5 May 2018 | nvidia dgx-1 nvlink hybrid cube-mesh.svg (file) | ![]() |
19 KB | Nvidia {{nvidia|NVLink}} configuration for the DGX-1. Diagram by WikiChip. | 1 |
03:05, 5 May 2018 | nvidia dgx-1 nvlink-gpu-xeon config.svg (file) | ![]() |
84 KB | fixed link going above others instead of under. | 2 |
17:00, 4 May 2018 | nvlink p100 intel cpu configs.svg (file) | ![]() |
109 KB | Nvidia {{nvidia|NVLink}} {{nvidia|P100}} with various configurations. Diagram by WikiChip. | 1 |
16:59, 4 May 2018 | nvlink p100 ibm p8+.svg (file) | ![]() |
45 KB | Nvidia {{nvidia|NVLink}} {{nvidia|P100}} with two IBM {{ibm|POWER8+|l=arch}} chips. Diagram by WikiChip. | 1 |
16:53, 4 May 2018 | nvlink p100.svg (file) | ![]() |
24 KB | Nvidia {{nvidia|NVLink}} {{nvidia|P100}} with a single xeons and two GPUs. Diagram by WikiChip. | 1 |
11:50, 4 May 2018 | nvlink link.svg (file) | ![]() |
91 KB | Nvidia {{nvidia|NVLink}} wires. Diagram by WikiChip. | 1 |
10:07, 4 May 2018 | nvidia gpu nvlink overview.svg (file) | ![]() |
14 KB | Nvidia {{nvidia|NVLink}} interconnect basic diagram by WikiChip. | 1 |
09:04, 4 May 2018 | nvidia gpu pcie bus.svg (file) | ![]() |
8 KB | Nviai dual-GPU on a PCIe bus. Diagram by WikiChip. | 1 |
22:41, 22 April 2018 | tci diagram.svg (file) | ![]() |
30 KB | ThruChip Interface diagram by WikiChip. | 1 |
21:33, 21 April 2018 | tci txrx graph.png (file) | ![]() |
143 KB | ThruChip Interface TX/RX. Image by ThruChip Communications. | 1 |
21:24, 21 April 2018 | tci h-bridge.svg (file) | ![]() |
43 KB | 2 | |
21:21, 14 April 2018 | amd 400 series storemi logo.png (file) | ![]() |
7 KB | AMD {{amd|400 Series Chipset}} ({{amd|Zen+|l=arch}} | 1 |
16:01, 12 April 2018 | qcs605.png (file) | ![]() |
922 KB | Qualcomm QCS605. Image by Qualcomm. | 1 |
04:06, 11 April 2018 | intel polaris tiling.png (file) | ![]() |
218 KB | Intel {{intel|Polaris|l=arch}} tiling. Image by Intel. | 1 |
03:21, 11 April 2018 | polaris high density bumps.png (file) | ![]() |
653 KB | Intel {{intel|Polaris|l=arch}} high-density bumps. Image by Intel. | 1 |
03:17, 11 April 2018 | polaris stacked diagram.png (file) | ![]() |
410 KB | Intel {{intel|Polaris|l=arch}} die stack diagram. Image by Intel. | 1 |
03:12, 11 April 2018 | intel polaris die 2.png (file) | ![]() |
618 KB | 2 | |
02:46, 11 April 2018 | polaris stacked.svg (file) | ![]() |
3.65 MB | Intel {{intel|Polaris|l=arch}} stacked dies diagram by WikiChip. | 1 |
02:14, 11 April 2018 | polaris (chip) block diagram.svg (file) | ![]() |
819 KB | 2 | |
02:06, 11 April 2018 | polaris block diagram.svg (file) | ![]() |
51 KB | Intel {{intel|Polaris|l=arch}} block diagram by WikiChip. | 1 |
08:26, 10 April 2018 | trc project.pdf (file) | ![]() |
1.39 MB | Intel Teraflops Research Chip - {{intel|Polaris}}. | 1 |
08:25, 10 April 2018 | teratec 07 intel.pdf (file) | ![]() |
1.47 MB | Intel {{intel|Polaris}}. * Aim High * Intel Technical Update * Teratec ’07 Symposium * June 20, 2007 * Stephen R. Wheat, Ph.D. * Director, HPC * Digital Enterprise Group | 1 |
08:24, 10 April 2018 | intel mpsoc 2007.pdf (file) | ![]() |
2.79 MB | Intel {{intel|Polaris}}, MPSoC 2007. | 1 |
07:34, 10 April 2018 | Tera Tera Tera 2006 davis.pdf (file) | ![]() |
2.74 MB | Intel {{intel|Polaris|l=arch}} Tera Tera Tera presnetation. | 1 |
07:17, 10 April 2018 | intel polaris core 2.png (file) | ![]() |
276 KB | Intel {{intel|Polaris|l=arch}} core die, Image by Intel. | 1 |
07:05, 10 April 2018 | intel polaris idf announcement.webm (file) | ![]() |
15.01 MB | Intel {{intel|Polaris|l=arch}} IDF announcement. | 1 |
23:56, 9 April 2018 | broadwell die (dual-core, 2).png (file) | ![]() |
3.75 MB | Intel {{intel|Broadwell|l=arch}} die shot. Image by Intel. | 1 |
First page |
Previous page |
Next page |
Last page |