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Date | Name | Thumbnail | Size | Description | Versions |
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19:53, 15 October 2017 | vrm circut with switching (multi-phase).svg (file) | ![]() |
31 KB | VRM switching with multi-phase. | 1 |
19:26, 15 October 2017 | vrm circut (multi-phase).svg (file) | ![]() |
37 KB | Multi-phase VRM circuit | 1 |
18:24, 15 October 2017 | vrm circut (high-side open).svg (file) | ![]() |
22 KB | VRM high-side open. | 1 |
18:24, 15 October 2017 | vrm circut (high-side closed).svg (file) | ![]() |
21 KB | VRM high-side closed. | 1 |
18:07, 15 October 2017 | vrm voltage 12v to 1p2v.svg (file) | ![]() |
26 KB | 2 | |
13:49, 15 October 2017 | vrm voltage at points a-b when high side switch is off-on.svg (file) | ![]() |
12 KB | 2 | |
13:06, 15 October 2017 | vrm voltage at points a-b when high side switch is on-off.svg (file) | ![]() |
12 KB | 2 | |
12:13, 15 October 2017 | vrm circut.svg (file) | ![]() |
30 KB | changed a bit for our explination | 3 |
23:28, 14 October 2017 | vrm general.svg (file) | ![]() |
19 KB | 2 | |
21:03, 12 September 2017 | a11 intro keynote event.png (file) | ![]() |
803 KB | Apple {{apple|A11}} intro slide from Apple's Keynote Event September 2017. | 1 |
14:12, 10 September 2017 | helio p23.png (file) | ![]() |
385 KB | 2 | |
14:12, 10 September 2017 | helio p30.png (file) | ![]() |
385 KB | 2 | |
14:48, 9 September 2017 | performance-2nd-generation-core-vpro-family-paper.pdf (file) | ![]() |
3.32 MB | 2nd Generation Intel® Core vPro Processor Family New levels of security, manageability, and responsiveness White Paper * 2nd Gen Intel® Core i7 vPro Processor * 2nd Gen Intel® Core i5 vPro Processor | 1 |
14:48, 9 September 2017 | performance-2nd-gen-core-product-brief.pdf (file) | ![]() |
1.54 MB | 2nd Generation Intel® Core vPro Processor Family | 1 |
14:48, 9 September 2017 | core-overview-of-2nd-generation-intel-core-processor-family-brief.pdf (file) | ![]() |
1.28 MB | 2nd Generation Intel® Core Processor Family | 1 |
12:43, 7 September 2017 | kirin 970 npu.png (file) | ![]() |
765 KB | NPU performance shown by Mr. Yu during 2017 IFA. Image from Huawei stream. | 1 |
23:47, 6 September 2017 | kirin 970.png (file) | ![]() |
1.76 MB | HiSilicon Kirin 970. Image by Huawei | 1 |
20:03, 6 September 2017 | hisilicon kirin logo.svg (file) | ![]() |
5 KB | HiSilicon {{hisil|Kirin}} logo | 1 |
11:02, 6 September 2017 | hisilicon k3v2 block.png (file) | ![]() |
54 KB | HiSilicon {{hisilicon|k3v2}} block diagram | 1 |
01:03, 6 September 2017 | hi3620.png (file) | ![]() |
35 KB | HiSilicon {{hisil|Hi3620}} | 1 |
00:16, 6 September 2017 | hisilicon k3v1 block.png (file) | ![]() |
341 KB | HiSilicon {{hisilicon|K3V1}} block diagram. | 1 |
23:30, 5 September 2017 | k3v1 prod brief.pdf (file) | ![]() |
151 KB | HiSilicon {{hisilicon|K3V1}} Product Brief | 1 |
23:21, 4 September 2017 | hisilicon logo.svg (file) | ![]() |
99 KB | HiSilicon logo | 1 |
23:38, 21 July 2017 | original COP2440 block diagram.png (file) | ![]() |
122 KB | National Semicondcutor {{national|COP2440}} original block diagram by National. | 1 |
17:12, 20 July 2017 | z14 core layout.png (file) | ![]() |
551 KB | IBM {{ibm|z14|l=arch}} core layout. Image by IBM. | 1 |
16:08, 2 July 2017 | core i9x logo.png (file) | ![]() |
540 KB | Intel {{intel|Core i9}}X logo, Introduced May 30, 2017 | 1 |
17:36, 24 June 2017 | arm1 pc.svg (file) | ![]() |
5 KB | The program counter of the {{armh|ARM1}} | 1 |
16:03, 24 June 2017 | arm1 pipeline.svg (file) | ![]() |
11 KB | slightly more detailed | 2 |
05:44, 23 June 2017 | PEZY Computing (March 7, 2017).pdf (file) | ![]() |
2.21 MB | PEZY computing; {{pezy|PEZY-SC2}}, {{pezy|PEZY-SC3}}, {{pezy|PEZY-SC4}} | 1 |
16:43, 8 June 2017 | skylake-sp memory.svg (file) | ![]() |
11 KB | Intel {{intel|Skylake|l=arch}}-SP New memory hierarchy. | 1 |
14:09, 6 June 2017 | amdahl's law by sequential portion.png (file) | ![]() |
202 KB | Amdahl's Law for 1 to 1024 cores based on percentage of sequential portion | 1 |
10:30, 1 June 2017 | tbmt software.jpg (file) | ![]() |
32 KB | Intel's {{intel|Turbo Boost Max Technology}} software. Image by Intel. | 1 |
00:35, 17 May 2017 | naples without heatspread.jpg (file) | ![]() |
44 KB | AMD's VP Forrest Norrod showing the 32-core Naples chip with the 4x Zepplines dies on a multi-chip package with the heat spreader off. | 1 |
00:31, 17 May 2017 | amd naples mcp.png (file) | ![]() |
77 KB | AMD {{amd|Naples|l=core}} MCP from AMD's Investor meeting | 1 |
00:11, 17 May 2017 | lisa announces epyc.png (file) | ![]() |
202 KB | AMD's CEO Lisa Su announces the {{amd|EPYC}} server processor family. Taken from AMD's investor's day stream. | 1 |
18:57, 16 May 2017 | ryzen threadripper.png (file) | ![]() |
425 KB | AMD {{amd|Ryzen}} ThreadRipper | 1 |
18:53, 16 May 2017 | amd zen2-3 roadmap.png (file) | ![]() |
541 KB | AMD {{amd|Zen 2}} and {{amd|Zen 3}} roadmap | 1 |
18:44, 16 May 2017 | amd epyc rodmap.png (file) | ![]() |
347 KB | AMD {{amd|EPYC}} roadmap, by AMD | 1 |
18:35, 7 May 2017 | intel xmp.png (file) | ![]() |
703 KB | Intel {{intel|XMP}} | 1 |
13:52, 7 May 2017 | haswell bclk.png (file) | ![]() |
249 KB | Intell {{intel|Haswell|l=arch}} BCLK | 1 |
13:52, 7 May 2017 | haswell oc chips.png (file) | ![]() |
322 KB | Intell {{intel|Haswell|l=arch}} OC Chips | 1 |
13:13, 7 May 2017 | Overclocking 6th Generation Intel® Core™ Processors.pdf (file) | ![]() |
4.22 MB | Overclocking {{intel|Skylake|6th Generation|l=arch}} Intel {{intel|Core}} Processors | 1 |
11:19, 7 May 2017 | skylake pcu.png (file) | ![]() |
126 KB | Intel {{intel|Skylake|l=arch}} PCU | 1 |
02:12, 7 May 2017 | skylake vrails.png (file) | ![]() |
198 KB | Intel {{intel|Skylake|l=arch}} Voltage Rails | 1 |
02:06, 7 May 2017 | skylake bclk block.png (file) | ![]() |
183 KB | Intel {{intel|Skylake|l=arch}} BCLK affected blocks. | 1 |
01:39, 7 May 2017 | skylake bclk.png (file) | ![]() |
212 KB | Intel {{intel|Skylake|l=arch}} BCLK | 1 |
00:01, 7 May 2017 | skylake overclock models chipset.png (file) | ![]() |
717 KB | Intel {{intel|Skylake|l=arch}} OC models & chipset | 1 |
02:26, 5 April 2017 | Mark-Bohr-2017-Moores-Law.pdf (file) | ![]() |
1.22 MB | Intel Technoogy & Manufacturing Day presentation, 10 nm / Moore's Law | 1 |
02:26, 5 April 2017 | Kaizad-Mistry-2017-Manufacturing.pdf (file) | ![]() |
813 KB | Intel Technoogy & Manufacturing Day presentation, 10 nm | 1 |
04:18, 4 April 2017 | intel 14nm++ (pmos).png (file) | ![]() |
130 KB | added units | 2 |
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