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- | process = 22 nm |l3 cache=6 MiB3 KB (399 words) - 16:27, 13 December 2017
- |core family=6 |process=14 nm4 KB (596 words) - 16:15, 13 December 2017
- |core family=6 |process=14 nm4 KB (596 words) - 16:15, 13 December 2017
- |core family=6 |process=14 nm4 KB (627 words) - 16:17, 13 December 2017
- |core family=6 |process=14 nm4 KB (627 words) - 16:20, 13 December 2017
- |core family=6 |process=14 nm4 KB (640 words) - 02:21, 16 January 2019
- |core family=6 |process=14 nm4 KB (650 words) - 02:21, 16 January 2019
- | process = 14 nm |l3 cache=6 MiB4 KB (407 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (401 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (395 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (424 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (405 words) - 16:22, 13 December 2017
- |process=14 nm |l3 cache=6 MiB4 KB (460 words) - 15:03, 24 March 2019
- |core family=6 |process=14 nm4 KB (631 words) - 16:18, 13 December 2017
- |core family=6 |process=14 nm4 KB (649 words) - 16:20, 13 December 2017
- | proc = 45 nm | proc 2 = 32 nm17 KB (2,292 words) - 09:32, 16 July 2019
- | proc = 800 nm | proc 2 = 600 nm10 KB (1,057 words) - 19:30, 1 November 2021
- | microarch 6 = Excavator | proc = 32 nm6 KB (700 words) - 15:43, 1 December 2019
- ...lithography process|28 nm process]] (HN) / [[22 nm lithography process|22 nm process]] (FN) in 2012. TSMC cancelled its planned 32nm node process. Intel's 32 nm process became the first process to introduce the [[self-aligned via patter10 KB (1,090 words) - 19:14, 8 July 2021
- ...e 14 nm node was introduced in 2014/2015 and has been replaced by the [[10 nm process]]. | process 1 lith = 193 nm17 KB (2,243 words) - 19:32, 25 May 2023