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From WikiChip
Gracemont - Microarchitectures - Intel
< intel | microarchitectures
Revision as of 23:05, 23 March 2020 by David (talk | contribs) (Reverted edits by 94.23.144.102 (talk) to last revision by 115.134.178.16)
| Edit Values | |
| Gracemont µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2021 |
| Process | 10 nm |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB, ENCLV, SHA |
| Succession | |
Gracemont is Intel's successor to Tremont, a 10 nm microarchitecture for ultra-low power devices and microservers.
Process Technology
Gracemont is designed to take advantage of Intel's 10 nm process.
Architecture
Key changes from Tremont
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/gracemont&oldid=96486"
Facts about "Gracemont - Microarchitectures - Intel"
| codename | Gracemont + |
| designer | Intel + |
| first launched | 2021 + |
| full page name | intel/microarchitectures/gracemont + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Gracemont + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |