Semiconductor & Computer Engineering
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Machine Learning Processor (MLP) - Microarchitectures - ARM
| Edit Values | |
| MLP µarch | |
| General Info | |
| Arch Type | NPU |
| Designer | Arm Holdings |
| Manufacturer | TSMC, Samsung, UMC |
| Introduction | 2018 |
| Process | 16 nm, 7 nm |
| PE Configs | 4, 8, 12, 16 |
Machine Learning Processor (MLP) is a first-generation neural processor microarchitecture designed by Arm for embedded and mobile SoCs. This microarchitecture is designed as a synthesizable NPU IP and is sold to other semiconductor companies to be implemented in their own chips.
Process technology
Although the MLP is designed as a synthesizable IP, it has been specifically tuned for the 16 nanometer and 7 nanometer nodes.
Release date
Arm officially released the MLP under the Ethos family in late 2019.
Architecture
Block diagram
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Overview
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See also
| codename | MLP + |
| designer | Arm Holdings + |
| first launched | 2018 + |
| full page name | arm holdings/microarchitectures/mlp + |
| instance of | microarchitecture + |
| manufacturer | TSMC +, Samsung + and UMC + |
| name | MLP + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) + |
| processing element count | 4 +, 8 +, 12 + and 16 + |