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From WikiChip
Rocket Lake - Microarchitectures - Intel
< intel | microarchitectures
| Edit Values | |
| Rocket Lake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Process | 14 nm |
| Core Configs | 4 |
| Pipeline | |
| Type | Superscalar, Superpipeline |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 14-19 |
| Decode | 5-way |
| Instructions | |
| ISA | x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX |
| Cache | |
| L1I Cache | 32 KiB/core 8-way set associative |
| L1D Cache | 32 KiB/core 8-way set associative |
| L2 Cache | 256 KiB/core 4-way set associative |
| L3 Cache | 2 MiB/core Up to 16-way set associative |
| L4 Cache | 128 MiB/package on Iris Pro GPUs only |
| Succession | |
Rocket Lake is a planned microarchitecture designed by Intel as a successor to Comet Lake for desktops and high-performance mobile devices.
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/rocket_lake&oldid=91882"
Facts about "Rocket Lake - Microarchitectures - Intel"
| codename | Rocket Lake + |
| core count | 4 + |
| designer | Intel + |
| full page name | intel/microarchitectures/rocket lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Rocket Lake + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |