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Cascade Lake SP - Cores - Intel
Edit Values | |
Cascade Lake SP | |
Skylake SP, Regular | |
Skylake SP, with HFI | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Introduction | May 16, 2017 (announced) Q4, 2018 (launched) |
Microarchitecture | |
ISA | x86-64 |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Word Size | 8 octets 64 bit16 nibbles |
Process | 14 nm 0.014 μm 1.4e-5 mm |
Technology | CMOS |
Packaging | |
Template:packages/intel/fclga-3647 | |
Succession | |
Cascade Lake SP (Cascade Lake Scalable Performance) is the code name for Intel's series of server multiprocessors based on the Cascade Lake microarchitecture as part of the Purley platform serving as the successor to Skylake SP. These chips support up to 8-way multiprocessing, up to 28 cores, and incorporate a new AVX512 x86 extension for neural network / deep learning workloads. Cascade Lake SP-based chips are manufactured on an enhanced 14nm++ process and utilize the Lewisburg chipset. Cascade Lake SP-based models are branded as the processor families: Xeon Bronze, Xeon Silver, Xeon Gold, and Xeon Platinum.
Facts about "Cascade Lake SP - Cores - Intel"
chipset | Lewisburg + |
designer | Intel + |
first announced | May 16, 2017 + |
first launched | April 2018 + |
instance of | core + |
isa | x86-64 + |
main image | + and + |
main image caption | Skylake SP, Regular + and Skylake SP, with HFI + |
manufacturer | Intel + |
microarchitecture | Cascade Lake + |
name | Cascade Lake SP + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |