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Ice Lake (server) µarch
General Info
Arch Type	CPU
Designer	Intel
Manufacturer	Intel
Introduction	2019
Process	10 nm
Instructions
ISA	x86-64
Cores
Core Names	Ice Lake SP, Ice Lake X
Succession
Cascade Lake Sapphire Rapids
Contemporary
Ice Lake (client)

Ice Lake (ICL) Server Configuration is Intel's successor to Cascade Lake, a 10 nm microarchitecture for enthusiasts and servers.

Codenames

Core	Abbrev	Target
Ice Lake X	ICL-X	High-end desktops & enthusiasts market
Ice Lake W	ICL-W	Enterprise/Business workstations
Ice Lake SP	ICL-SP	Server Scalable Processors

Process Technology

See also: Ice Lake (client) § Process Technology

Ice Lake will use a second-generation enhanced 10 nm process called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.

Compiler support

Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.

Compiler	Arch-Specific	Arch-Favorable
ICC	-march=icelake	-mtune=icelake
GCC	-march=icelake	-mtune=icelake
LLVM	-march=icelake	-mtune=icelake
Visual Studio	/?	/tune:?

CPUID

Core	Extended Family	Family	Extended Model	Model
?	0	0x6	0x?	?
	Family 6 Model ?
?	0	0x6	?	?
	Family 6 Model ?

Architecture

Not much is known about Ice Lake's architecture.

Key changes from Cascade Lake

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

• Enhanced "10nm+" (from 14 nm)

New instructions

Ice Lake introduced a number of new instructions:

• CLWB - Force cache line write-back without flush
• RDPID - Read Processor ID
• Additional AVX-512 extensions:
  • AVX512VPOPCNTDQ - AVX-512 Vector Population Count Doubleword and Quadword
  • AVX512VNNI - AVX-512 Vector Neural Network Instructions
  • AVX512GFNI - AVX-512 Galois Field New Instructions
  • AVX512VAES - AVX-512 Vector AES
  • AVX512VBMI2 - AVX-512 Vector Bit Manipulation, Version 2
  • AVX512BITALG - AVX-512 Bit Algorithms
  • AVX512VPCLMULQDQ - AVX-512 Vector Vector Carry-less Multiply
• TME - Total Memory Encryption
• ENCLV - SGX oversubscription instructions
• Fast Short REP MOV
• Split Lock Detection

All Ice Lake Chips

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

	List of Ice Lake Processors
	Main processor									Frequency/Turbo		Mem	Major Feature Diff
Model	Launched	Price	Family	Core Name	Cores	Threads	L2$	L3$	TDP	Frequency	Max Turbo	Max Mem	Turbo	SMT
	Uniprocessors
	Multiprocessors (2-way)
	Multiprocessors (4-way)
	Multiprocessors (8-way)
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