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From WikiChip
Tiger Lake - Microarchitectures - Intel
< intel | microarchitectures
| Edit Values | |
| Tiger Lake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2019 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
| Contemporary | |
| Sapphire Rapids | |
Tiger Lake (TGL) is Intel's successor to Ice Lake, an enhanced 10nm++ process microarchitecture for mainstream workstations, desktops, and mobile devices.
Process Technology
- Main article: Cannon Lake § Process Technology
Tiger Lake is set to use the same 10 nm process that was designed for Cannon Lake.
Architecture
Not much is known about Tiger Lake's architecture.
Key changes from Ice Lake
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/tiger_lake&oldid=76764"
Facts about "Tiger Lake - Microarchitectures - Intel"
| codename | Tiger Lake + |
| designer | Intel + |
| first launched | 2019 + |
| full page name | intel/microarchitectures/tiger lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tiger Lake + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |