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From WikiChip
Mongoose 3 (M3) - Microarchitectures - Samsung
< samsung
| Edit Values | |
| Mongoose 3 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Samsung |
| Manufacturer | Samsung |
| Process | 10 nm |
| Pipeline | |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Decode | 6-way |
| Instructions | |
| ISA | ARMv8 |
| Cache | |
| L1I Cache | 64 KiB/core 4-way set associative |
| L1D Cache | 32 KiB/core 8-way set associative |
| L2 Cache | 2 MiB/cluster 16-way set associative |
| Succession | |
Mongoose 3 (M3) is an ARM microarchitecture designed by Samsung for their consumer electronics serving as a successor to the Mongoose 2.
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/microarchitectures/m3&oldid=73688"
Facts about "Exynos M3 - Microarchitectures - Samsung"
| codename | Mongoose 3 + |
| designer | Samsung + |
| full page name | samsung/microarchitectures/m3 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 + |
| manufacturer | Samsung + |
| microarchitecture type | CPU + |
| name | Mongoose 3 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |