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From WikiChip
Mongoose 2 (M2) - Microarchitectures - Samsung
< samsung
| Edit Values | |
| Mongoose 2 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Samsung |
| Manufacturer | Samsung |
| Process | 10 nm |
| Pipeline | |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Decode | 4-way |
| Instructions | |
| ISA | ARMv8 |
| Cache | |
| L1I Cache | 64 KiB/core 4-way set associative |
| L1D Cache | 32 KiB/core 8-way set associative |
| L2 Cache | 2 MiB/cluster 16-way set associative |
| Succession | |
Mongoose 2 (M2) is an ARM microarchitecture designed by Samsung for their consumer electronics serving as a successor to the Mongoose 1.
Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/microarchitectures/m2&oldid=73683"
Facts about "Exynos M2 - Microarchitectures - Samsung"
| codename | Mongoose 2 + |
| core count | 4 + |
| designer | Samsung + |
| first launched | February 23, 2017 + |
| full page name | samsung/microarchitectures/m2 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 + |
| manufacturer | Samsung + |
| microarchitecture type | CPU + |
| name | Mongoose 2 + |
| phase-out | 2018 + |
| pipeline stages | 14 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |