From WikiChip
Xeon Phi 7295 - Intel
Edit Values | |
Xeon Phi 7295 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 7295 |
Part Number | HJ8068303823700 |
S-Spec | SR3VD |
Market | Workstation, Server, Supercomputer |
Introduction | December 18, 2017 (announced) December 18, 2017 (launched) |
Shop | Amazon |
General Specs | |
Family | Xeon Phi |
Series | x205 |
Locked | Yes |
Frequency | 1,500 MHz |
Turbo Frequency | 1,600 MHz (1 core) |
Clock multiplier | 15 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Knights Mill |
Core Stepping | A0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 72 |
Threads | 288 |
Max Memory | 384 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Vcore | 0.55 V-1.2 V |
TDP | 320 W |
Tcase | 0 °C – 77 °C |
Packaging | |
Template:packages/intel/fclga-3647 |
Xeon Phi 7295 is a 72-core x86 many-core microprocessor introduced by Intel in late 2017 specifically designed to accelerate artificial intelligence workloads. This processor, which is fabricated on their own 14 nm process based on the Knights Mill microarchitecture, operates at a frequency of 1.5 GHz with a TDP of 320 W and a turbo of 1.6 GHz.
Cache
- Main article: Knights Mill § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||
|
Memory controller
Integrated Memory Controller
|
||||||||||||||
|
Facts about "Xeon Phi 7295 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Phi 7295 - Intel#pcie + |
base frequency | 1,500 MHz (1.5 GHz, 1,500,000 kHz) + |
clock multiplier | 15 + |
core count | 72 + |
core stepping | A0 + |
core voltage (max) | 1.2 V (12 dV, 120 cV, 1,200 mV) + |
core voltage (min) | 0.55 V (5.5 dV, 55 cV, 550 mV) + |
designer | Intel + |
family | Xeon Phi + |
first announced | December 18, 2017 + |
first launched | December 18, 2017 + |
full page name | intel/xeon phi/7295 + |
has ecc memory support | true + |
has locked clock multiplier | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 4,608 KiB (4,718,592 B, 4.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 2,304 KiB (2,359,296 B, 2.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 2,304 KiB (2,359,296 B, 2.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 36 MiB (36,864 KiB, 37,748,736 B, 0.0352 GiB) + |
ldate | December 18, 2017 + |
main image | + |
manufacturer | Intel + |
market segment | Workstation +, Server + and Supercomputer + |
max case temperature | 350.15 K (77 °C, 170.6 °F, 630.27 °R) + |
max cpu count | 1 + |
max memory | 393,216 MiB (402,653,184 KiB, 412,316,860,416 B, 384 GiB, 0.375 TiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
microarchitecture | Knights Mill + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 7295 + |
name | Xeon Phi 7295 + |
part number | HJ8068303823700 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
s-spec | SR3VD + |
series | x205 + |
smp max ways | 1 + |
supported memory type | DDR4-2400 + |
tdp | 320 W (320,000 mW, 0.429 hp, 0.32 kW) + |
technology | CMOS + |
thread count | 288 + |
turbo frequency (1 core) | 1,600 MHz (1.6 GHz, 1,600,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |