RISC-V
Instruction Set Architecture

General

• History
• Families

Base Variants(base)

• RV32
• RV64
• RV128

Standard Extensions(all)

• A
• B
• C
• D
• E
• F
• G
• I
• J
• L
• M
• N
• P
• Q
• T
• V

Topics

• Foundation
• Non-Standard Extensions
• Addressing Modes
• Registers
• Assembly
• Interrupts
• Microarchitectures

RISC-V (pronounced risk-five) is a free and open instruction set architecture standardized by the RISC-V Foundation that is specifically designed to enable configurability, modularity, and extensibility. RISC-V is not designed to replace prominent ISAs such as x86 and ARM, but rather to provide a foundation for emerging classes of processors and accelerators that require a base ISA on top of which additional functionality can be added.

Overview

RISC-V is a free and open ISA; no license is needed to be obtained and the use of the ISA royalty-free for anyone. RISC-V is designed to provide a foundation or a base architecture for companies and researchers who need it in order to be able to augment their own technology (e.g., customer accelerators, fixed function hardware, and other domain-specific additions) on top of it. RISC-V provides a base architecture (offered in 3 flavors of 32/64/128 bit) consisting of less than 50 instructions which is capable of running a full software stack including a full-fledged operating system. The core instructions are frozen and are guaranteed to never change. In addition to the core instructions, RISC-V provides a number of optional standard extensions that can be implemented or omitted depending on the designer goals. Other than the standard extensions RISC-V also reserves opcodes to be custom tailored by chip designers for their own applications.