Template:mpu Core i5-9500 is a planned 64-bit mid-range performance x86 desktop processor by Intel set to be introduced in 2018. The i5-9400 is fabricated on Intel's 2nd generation 10nm+ process based on the Ice Lake microarchitecture.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Leaked Info! Some of the information presented in this article is solely based on leaks that were published online or obtained directly by WikiChip. It goes without saying that this information could change, be incomplete, wrong, or even made up. It's highly advised to wait for an official product announcement.

Cache

Main article: Ice Lake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 512 KiB 524,288 B 0.5 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 8-way set associative   L1D$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 8-way set associative write-back L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     8x256 KiB 4-way set associative write-back L3$ 12 MiB 12,288 KiB 12,582,912 B 0.0117 GiB     6x2 MiB 16-way set associative write-back