Template:mpu Atom C3955 is a 64-bit hexadeca-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3955, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 2.1 GHz with a TDP of 32 W and a turbo boost frequency of up to 2.4 GHz. The C3955 supports up to a dual-channel of 256 GiB of DDR4-2400 ECC memory.

Cache

Main article: Goldmont § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 896 KiB 917,504 B 0.875 MiB L1I$ 512 KiB 524,288 B 0.5 MiB 16x32 KiB 8-way set associative write-back L1D$ 384 KiB 393,216 B 0.375 MiB 16x24 KiB 6-way set associative write-back L2$ 16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB     8x2 MiB 16-way set associative write-back