Template:mpu Xeon Platinum 8170M is a 64-bit 26-core x86 multi-socket highest performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8170M, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.1 GHz with a TDP of 165 W and a turbo boost frequency of up to 3.7 GHz, supports up 1.5 TiB of hexa-channel DDR4-2666 ECC memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1.625 MiB 1,664 KiB 1,703,936 B L1I$ 832 KiB 851,968 B 0.813 MiB 26x32 KiB 8-way set associative   L1D$ 832 KiB 851,968 B 0.813 MiB 26x32 KiB 8-way set associative write-back L2$ 26 MiB 26,624 KiB 27,262,976 B 0.0254 GiB     26x1 MiB 16-way set associative write-back L3$ 35.75 MiB 36,608 KiB 37,486,592 B 0.0349 GiB     26x1.375 MiB 11-way set associative write-back