Template:mpu Xeon Platinum 8168 is a 64-bit 24-core x86 multi-socket highest performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8168, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.7 GHz with a TDP of 205 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1.5 MiB 1,536 KiB 1,572,864 B L1I$ 768 KiB 786,432 B 0.75 MiB 24x32 KiB 8-way set associative   L1D$ 768 KiB 786,432 B 0.75 MiB 24x32 KiB 8-way set associative write-back L2$ 24 MiB 24,576 KiB 25,165,824 B 0.0234 GiB     24x1 MiB 16-way set associative write-back L3$ 33 MiB 33,792 KiB 34,603,008 B 0.0322 GiB     24x1.375 MiB 11-way set associative write-back