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    Xeon Gold 6126  - Intel    
                	
														Template:mpu Xeon Gold 6126 is a 64-bit octa-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6126, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.6 GHz with a TDP of 125 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Cache
- Main article: Skylake § Cache
|  | Cache Organization  Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. | ||||||||||||||||||||||||||||||||||||
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Memory controller
|  | Integrated Memory Controller | |||||||||||
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Features
[Edit/Modify Supported Features]
Facts about "Xeon Gold 6126  - Intel"
| has advanced vector extensions | true + | 
| has advanced vector extensions 2 | true + | 
| has ecc memory support | true + | 
| has extended page tables support | true + | 
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions + and OS Guard + | 
| has intel enhanced speedstep technology | true + | 
| has intel supervisor mode execution protection | true + | 
| has intel vpro technology | true + | 
| has intel vt-d technology | true + | 
| has intel vt-x technology | true + | 
| has second level address translation support | true + | 
| has simultaneous multithreading | true + | 
| has transactional synchronization extensions | true + | 
| has x86 advanced encryption standard instruction set extension | true + | 
| l1$ size | 768 KiB (786,432 B, 0.75 MiB) + | 
| l1d$ description | 8-way set associative + | 
| l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + | 
| l1i$ description | 8-way set associative + | 
| l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + | 
| l2$ description | 16-way set associative + | 
| l2$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + | 
| l3$ description | 11-way set associative + | 
| l3$ size | 16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) + | 
| max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + | 
| max memory channels | 6 + | 
| supported memory type | DDR4-2666 + | 
| x86/has memory protection extensions | true + | 
