Template:mpu The Athlon MP 2600+ (OPN AMSN2600DKT3C) based on the Thoroughbred core was a 32-bit x86 multiprocessor developed by AMD and introduced in late 2002 for the server and workstation market. This MPU operated at 2.1 GHz with a FSB transfer rate of 266 MT/s (x16 multiplier), was manufactured on a newer 130 nm copper processor technology in Fab 30 in Dresden, Germany.

Cache

Main article: K7 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 1x64 KiB 2-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 1x64 KiB 2-way set associative   L2$ 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB     1x256 KiB 16-way set associative

Graphics

This MPU has no integrated graphics processing unit.

Features

[Edit/Modify Supported Features]

	Supported x86 Extensions & Processor Features
	MMX MMX Extension EMMX Extended MMX Extension 3DNow! 3DNow! Extension E3DNow! Extended 3DNow! Extension SSE Streaming SIMD Extensions x86-16 16-bit x86 x86-32 32-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU SmartMP SmartMP Technology

• Advanced Configuration and Power Interface
  • Halt State
  • Stop Grant State

Documents

Datasheets

• AMD Athlon MP Processor Model 8 Data Sheet for Multiprocessor Platforms; Publication # 25722 Rev. E; Issue Date: March 2003.

Others

• System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors; Publication # 25325; Rev: B; August 2002.