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From WikiChip
Alpha 21264 - Microarchitectures - DEC
< dec
| Edit Values | |
| Alpha 21264 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | DEC |
| Manufacturer | DEC, Intel |
| Introduction | February, 1998 |
| Process | 0.35 µm |
| Core Configs | 1 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 6 |
| Decode | 4-way |
| Instructions | |
| ISA | Alpha |
| Cache | |
| L1I Cache | 64 KiB/core 2-way set associative |
| L1D Cache | 64 KiB/core 2-way set associative |
| Succession | |
Retrieved from "https://en.wikichip.org/w/index.php?title=dec/microarchitectures/alpha_21264&oldid=44378"
Facts about "Alpha 21264 - Microarchitectures - DEC"
| codename | Alpha 21264 + |
| core count | 1 + |
| designer | DEC + |
| first launched | February 1998 + |
| full page name | dec/microarchitectures/alpha 21264 + |
| instance of | microarchitecture + |
| instruction set architecture | Alpha + |
| manufacturer | DEC +, Intel + and Samsung + |
| microarchitecture type | CPU + |
| name | Alpha 21264 + |
| pipeline stages | 6 + |
| process | 350 nm (0.35 μm, 3.5e-4 mm) + |