Template:mpu Xeon Gold 6134 is a 64-bit x86 high-performance server octadeca-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 6134 operates at 3.2 GHz.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1.125 MiB 1,152 KiB 1,179,648 B L1I$ 576 KiB 589,824 B 0.563 MiB 18x32 KiB 8-way set associative   L1D$ 576 KiB 589,824 B 0.563 MiB 18x32 KiB 8-way set associative write-back L2$ 18 MiB 18,432 KiB 18,874,368 B 0.0176 GiB     18x1 MiB 16-way set associative write-back L3$ 24.75 MiB 25,344 KiB 25,952,256 B 0.0242 GiB     18x1.375 MiB 11-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2666 Supports ECC Yes Controllers 1 Channels 6 Max Bandwidth 119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s Bandwidth Single 19.89 GiB/s Double 39.72 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s