Template:mpu Ryzen 5 1600 is a 64-bit hexa-core mid-range performance x86 desktop microprocessor set to be introduced by AMD in early 2017. This processor is based on AMD's Zen microarchitecture and is fabricated on a 14 nm process. The 1600 operates at a base frequency of 3.2 GHz with a TDP of 65 W and a Boost frequency of 3.6 GHz. This model is a less overclockable friendly version of the 1600X. This MPU supports up to 64 GiB of dual-channel DDR4-2666 ECC memory.

Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 576 KiB 589,824 B 0.563 MiB L1I$ 384 KiB 393,216 B 0.375 MiB 6x64 KiB 4-way set associative   L1D$ 192 KiB 196,608 B 0.188 MiB 6x32 KiB 8-way set associative write-back L2$ 3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB     6x512 KiB 8-way set associative write-back L3$ 16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB     2x8 MiB 16-way set associative

Memory controller

This processors supports 2 DDR4 PHYs, each supporting 1 channel of 64-bit data plus ECC with 2 DIMMs per channel. DIMMs of rates 1,333 MT/s - 3,200 MT/s are supported (UDIMM/SODIMM).

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-3200 Supports ECC Yes Max Mem 64 GiB Controllers 2 Channels 2 Max Bandwidth 39.74 GiB/s 40,693.76 MiB/s 42.671 GB/s 42,670.5 MB/s 0.0388 TiB/s 0.0427 TB/s Bandwidth Single 19.87 GiB/s Double 39.74 GiB/s

[Edit] Memory Configurations
Dual Channel	Single Rank	2 DIMMs	DDR4-2666
		4 DIMMs	DDR4-2133
	Double Rank	2 DIMMs	DDR4-2400
		4 DIMMs	DDR4-1866

Expansions

The Ryzen 5 1600 includes 20 PCIe lanes supporting Gen1, Gen2, and Gen3: 16 for a DGP and 4 for storage (NVMe or 2 ports SATA Express). PHY of 16 lanes may each have a maximum of 8 PCIe ports (x1, x2, x4, x8, x16). An additional 6 x4 PHYs plus 5 x2 PHYs supporting PCIe, WAFL, xGMI, SATA and Ethernet (See networking below).

[Edit/Modify Expansions Info]

	Expansion Options
	PCIe Revision 3.0 Max Lanes 20 Configs 2x8+1x4 USB Revision 3.0, 2.0 Ports 4 Rate 5 Gbit/s UART Ports 4 SATA Revision 3.0 Ports 4 GP I/O 6 ports

• eMMC, LPC, SMBus, SPI/eSPI

Networking

PHYs support for up to 4 lanes of 10/100/1000 SGMII, or 10GBASE-KR, or 1000BASE-KX Ethernet operation.

[Edit/Modify Network Info]

	Networking
	Ethernet 1 GigE Yes (Ports: 4) 10GbE Yes (Ports: 4) MII RGMII Yes (Ports: 4)

Audio

Support Azalia High Definition Audio

Graphics

This processor has no integrated graphics.

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 SSE4a Streaming SIMD Extensions 4a AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG SHA SHA Extensions ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute SMT Simultaneous Multithreading AMD-Vi AMD-Vi (I/O MMU virtualization) AMD-V AMD Virtualization SenseMI SenseMI Technology

• This model has partial XFR support, allowing for an additional +50 MHz boost frequency.