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From WikiChip
POWER9 - Microarchitectures - IBM
< ibm
| Edit Values | |
| POWER9 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | IBM |
| Manufacturer | GlobalFoundries |
| Introduction | 2H, 2017 |
| Phase-out | 2h, 2018 |
| Process | 14 nm |
| Pipeline | |
| Type | Superscalar |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | Power |
| Cache | |
| L1I Cache | 32 KiB/core |
| L1D Cache | 32 KiB/core |
| L2 Cache | 512 KiB/core |
| L3 Cache | 120 MiB/chip |
| Succession | |
POWER9 is the 14 nm microarchitecture for IBM's family of POWER9 processors set to be introduced in the 2nd half of 2017. POWER9 is a successor to the POWER8 microarchitecture.
 |
This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information. |
Retrieved from "https://en.wikichip.org/w/index.php?title=ibm/microarchitectures/power9&oldid=38720"
Facts about "POWER9 - Microarchitectures - IBM"
| codename | POWER9 + |
| core count | 4 +, 8 +, 12 +, 16 +, 20 + and 24 + |
| designer | IBM + |
| first launched | August 2017 + |
| full page name | ibm/microarchitectures/power9 + |
| instance of | microarchitecture + |
| instruction set architecture | Power ISA v3.0B + |
| manufacturer | GlobalFoundries + |
| microarchitecture type | CPU + |
| name | POWER9 + |
| phase-out | 2020 + |
| pipeline stages (max) | 16 + |
| pipeline stages (min) | 12 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |