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From WikiChip
Tigerlake - Microarchitectures - Intel
< intel | microarchitectures
| Edit Values | |
| Tigerlake µarch | |
| General Info |
Tigerlake is a planned microarchitecture by Intel as a successor to Icelake. Tigerlake is expected to be fabricated using a 10 nm process. Tigerlake is the "Optimization" microarchitecture as part of Intel's PAO model.
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/tiger_lake&oldid=24850"
Facts about "Tiger Lake - Microarchitectures - Intel"
| codename | Tigerlake + |
| designer | Intel + |
| first launched | 2019 + |
| full page name | intel/microarchitectures/tiger lake + |
| instance of | microarchitecture + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tigerlake + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |