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i486SX2-50 - Intel
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Template:mpu i486SX2-50 was a fourth-generation x86 microprocessor introduced by Intel in the early 1990s. This chip, which is based on the 80486 microarchitecture, had a clock doubler operating at 50 MHz, twice the bus speed. In contrast to the i486DX chips, the i486SX line had no functional FPU on-die.

Cache

Main article: 80486 § Cache
Cache Info [Edit Values]
L1$ 8 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x8 KB 4-way set associative (unified, write-through policy)

Graphics

This chip had no integrated graphics processing unit.

Features

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/80486/486sx2-50&oldid=18499"
Facts about "i486SX2-50 - Intel"
RDF feed
base frequency50 MHz (0.05 GHz, 50,000 kHz) +
bus rate25 MT/s (0.025 GT/s, 25,000 kT/s) +
bus speed25 MHz (0.025 GHz, 25,000 kHz) +
bus typeFSB +
clock multiplier2 +
core count1 +
core name486SX2 +
core voltage5 V (50 dV, 500 cV, 5,000 mV) +
core voltage tolerance5% +
cpuid45B +
designerIntel +
family80486 +
full page nameintel/80486/486sx2-50 +
instance ofmicroprocessor +
l1$ description4-way set associative +
l1$ size8 KiB (8,192 B, 0.00781 MiB) +
ldate1900 +
main imageFile:KL intel i486SX2.jpg +
main image captionA80486SX2-50, S-Spec SX845 +
manufacturerIntel +
max cpu count1 +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max operating temperature85 °C +
microarchitecture80486 +
min operating temperature0 °C +
model numberi486SX2-50 +
nameIntel i486SX2-50 +
part numberA80486SX2-50 + and A80486SX250 +
power dissipation3.08 W (3,080 mW, 0.00413 hp, 0.00308 kW) +
process800 nm (0.8 μm, 8.0e-4 mm) +
s-specSX845 +
s-spec (qs)Q0498 + and Q0576 +
series486SX2 +
smp max ways1 +
technologyCMOS +
transistor count900,000 +
word size32 bit (4 octets, 8 nibbles) +