Edit Values | |
Cascade Lake SP | |
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General Info | |
Designer | Intel |
Manufacturer | Intel |
Introduction | February 24, 2020 (announced) February 24, 2020 (launched) |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Word Size | 8 octets 64 bit16 nibbles |
Process | 14 nm 0.014 μm 1.4e-5 mm |
Technology | CMOS |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Contemporary | |
Cascade Lake SP |
Cascade Lake R (Cascade Lake Scalable Performance Refresh) is code name for Intel's series of server multiprocessors based on the Cascade Lake microarchitecture as part of the Purley platform serving as mid-cycle refresh to Cascade Lake SP. Cascade Lake R only targets mainstream entry and mid-range servers and therefore only support up to 2-way multiprocessing. As with Cascade Lake SP, these chips also support up to 28 cores, incorporate AVX512 x86 extension for neural network / deep learning workloads, and introduces persistent memory support. Cascade Lake R-based chips are manufactured on an enhanced 14 nm process and utilize the Lewisburg chipset.
Cascade Lake R-based models are branded as the 2nd-generation Xeon Bronze, Xeon Silver, and Xeon Gold processor families.
chipset | Lewisburg + |
designer | Intel + |
first announced | February 24, 2020 + |
first launched | February 24, 2020 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
main image | ![]() |
manufacturer | Intel + |
microarchitecture | Cascade Lake + |
name | Cascade Lake R + |
package | FCLGA-3647 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | Socket P + and LGA-3647 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |