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Spring Hill - Intel
Edit Values | |
Spring Hill µarch | |
General Info | |
Arch Type | NPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | May, 2019 |
Process | 10 nm |
Core Configs | 2 |
PE Configs | 8, 10, 12 |
Cache | |
L3 Cache | 3 MiB/Slice |
Spring Hill is a 10 nm microarchitecture designed by Intel for their inference neural processors. Spring Hill was developed by the Israel Haifa Development Center (IDC).
Spring Hill-based products are branded as the NNP-I 1000 series.
Contents
Process technology
Spring Hill NPUs are fabricated on Intel's 10 nm process.
Architecture
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Block Diagram
SoC Overview
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Sunny Cove Core
See Sunny Cove § Block diagram.
Inference Engine (ICE)
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Memory Organization
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Overview
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Inference Engine (ICE)
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Board
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Die
- 10 nm process
- 8,500,000,000 transistors
- 239 mm² die size
Facts about "Spring Hill - Microarchitectures - Intel"
codename | Spring Hill + |
core count | 2 + |
designer | Intel + |
first launched | May 2019 + |
full page name | intel/microarchitectures/spring hill + |
instance of | microarchitecture + |
manufacturer | Intel + |
name | Spring Hill + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |
processing element count | 8 +, 10 + and 12 + |