Edit Values

General Info

Microarchitecture

A4-9120C is a 64-bit dual-core ultra-low power x86 mobile microprocessor introduced by AMD in early 2019. This processor is based on AMD's Excavator microarchitecture and is fabricated on a 28 nm process. The A4-9120C operates at a base frequency of 1.6 GHz with a TDP of 6 W and a turbo frequency of 2.4 GHz. This APU supports single-channel DDR4-1866 memory and incorporates Radeon R4 series graphics operating at up to 600 MHz.

Cache

Main article: Excavator § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 160 KiB 163,840 B 0.156 MiB L1I$ 96 KiB 98,304 B 0.0938 MiB 1x96 KiB     L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB     L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     2x1 MiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-1866 Supports ECC No Controllers 1 Channels 1 Max Bandwidth 13.91 GiB/s 14,243.84 MiB/s 14.936 GB/s 14,935.749 MB/s 0.0136 TiB/s 0.0149 TB/s Bandwidth Single 13.91 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 8 Configuration: 1x8