From WikiChip
A6-9920C - AMD
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General Info | |
Microarchitecture |
A6-9920C is a 64-bit dual-core ultra-low power x86 mobile microprocessor introduced by AMD in early 2019. This processor is based on AMD's Excavator microarchitecture and is fabricated on a 28 nm process. The A6-9920C operates at a base frequency of 1.8 GHz with a TDP of 6 W and a turbo frequency of 2.7 GHz. This APU supports single-channel DDR4-1866 memory and incorporates Radeon R5 series graphics operating at up to 720 MHz.
Cache
- Main article: Excavator § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options |
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Facts about "A6-9220C - AMD"
full page name | amd/a6/a6-9220c + |
instance of | microprocessor + |
ldate | 1900 + |