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Cortex-A5 - Microarchitectures - ARM
Edit Values | |
Cortex-A5 µarch | |
General Info | |
Arch Type | CPU |
Designer | ARM Holdings |
Manufacturer | TSMC |
Introduction | October 22, 2009 |
Instructions | |
ISA | ARMv7 |
Succession | |
Cortex-A5 (codename Sparrow) is the successor to the Cortex-A9, an ultra-low power ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
Contents
Architecture
Key changes from Cortex-A9
- New in-order pipeline (form out-of-order)
- Shorter pipeline (8, up from 9-12)
- 0.5x frequency (1 GHz, down from 2 GHz)
- Single-issue (from dual-issue)
- Shorter pipeline (8, up from 9-12)
- Reduced return stack size (4 entries, down from 8)
- Integer
- Hardware Fused Multiply-Accumulate
- VFPv4 (from VFPv3)
- Memory subsystem
- Level 1 instruction cache reduced to 2-way set associative (down from 4-way)
This list is incomplete; you can help by expanding it.
Block Diagram
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Memory Hierarchy
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Licensees
Arm named the following companies as licensees.
Facts about "Cortex-A5 - Microarchitectures - ARM"
codename | Cortex-A5 + |
designer | ARM Holdings + |
first launched | October 22, 2009 + |
full page name | arm holdings/microarchitectures/cortex-a5 + |
instance of | microarchitecture + |
instruction set architecture | ARMv7 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-A5 + |