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From WikiChip
Ares - Microarchitectures - ARM
Edit Values | |
Ares µarch | |
General Info | |
Arch Type | CPU |
Designer | ARM Holdings |
Manufacturer | TSMC |
Process | 10 nm, 7 nm |
Pipeline | |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Ares is a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/neoverse_n1&oldid=84904"
Facts about "Neoverse N1 - Microarchitectures - ARM"
codename | Ares + |
designer | ARM Holdings + |
full page name | arm holdings/microarchitectures/neoverse n1 + |
instance of | microarchitecture + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Ares + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) + |