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Amber Lake - Microarchitectures - Intel
Edit Values | |
Amber Lake µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | June, 2018 |
Process | 14 nm |
Core Configs | 2 |
Pipeline | |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 14-19 |
Decode | 5-way |
Instructions | |
ISA | x86-64 |
Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX |
Cache | |
L1I Cache | 32 KiB/core 8-way set associative |
L1D Cache | 32 KiB/core 8-way set associative |
L2 Cache | 256 KiB/core 4-way set associative |
L3 Cache | 2 MiB/core Up to 16-way set associative |
Cores | |
Core Names | Whiskey Lake U |
Succession | |
Contemporary | |
Coffee Lake Whiskey Lake Cannon Lake |
Amber Lake (AML) is a microarchitecture designed by Intel as a successor to Kaby Lake for extremely-low power mobile devices, launched concurrently with Coffee Lake and Whiskey Lake.
Contents
Codenames
Core | Abbrev | Description | Graphics | Target |
---|---|---|---|---|
Amber Lake Y | AML-Y | Extremely-low power | GT2 | Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
Brands
This section is empty; you can help add the missing info by editing this page. |
Release Dates
Amber Lake was introduced at Computex 2018 on June 5.
Technology
Amber Lake is fabricated on 3rd generation improved 14++ process.
Compatibility
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Compiler support
Compiler | Arch-Specific | Arch-Favorable |
---|---|---|
ICC | -march=skylake |
-mtune=skylake
|
GCC | -march=skylake |
-mtune=skylake
|
LLVM | -march=skylake |
-mtune=skylake
|
Visual Studio | /arch:AVX2 |
/tune:skylake
|
CPUID
Core | Extended Family |
Family | Extended Model |
Model |
---|---|---|---|---|
Y | 0 | 0x6 | ? | ? |
Family 6 Model ? |
Architecture
Key changes from Kaby Lake
This section is empty; you can help add the missing info by editing this page. |
Overview
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Facts about "Amber Lake - Microarchitectures - Intel"
codename | Amber Lake + |
core count | 2 + |
designer | Intel + |
first launched | June 2018 + |
full page name | intel/microarchitectures/amber lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Amber Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |