From WikiChip
A1 - Ampere
a1
| Edit Values | |||||||
| A1 | |||||||
| General Info | |||||||
| Designer | Ampere Computing | ||||||
| Manufacturer | TSMC | ||||||
| Model Number | A1 | ||||||
| Market | Server | ||||||
| Introduction | February 5, 2018 (announced) | ||||||
| Release Price | $950 | ||||||
| General Specs | |||||||
| Turbo Frequency | 3,300 MHz | ||||||
| Microarchitecture | |||||||
| ISA | ARMv8 (ARM) | ||||||
| Process | 16 nm | ||||||
| Technology | CMOS | ||||||
| Word Size | 64 bit | ||||||
| Cores | 32 | ||||||
| Threads | 32 | ||||||
| Max Memory | 1 TiB | ||||||
| Multiprocessing | |||||||
| Max SMP | 1-Way (Uniprocessor) | ||||||
| Electrical | |||||||
| Vcore | 0.85 V | ||||||
| VI/O | 1.8, 3.3 | ||||||
| TDP | 125 W | ||||||
| Tjunction | 0 °C – 90 °C | ||||||
| Packaging | |||||||
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A1 is a 64-bit 32-core ARM server microprocessor introduced by Ampere in 2018. Fabricated on TSMC's 16FF+, this processor operates at ? with a turbo frequency of up to 3.3 GHz and 125 W TDP. This processor supports up to 8 channels of DDR4-2666 ECC memory.
Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
Expansion Options |
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Facts about "eMAG 8180 - Ampere"
| full page name | ampere computing/emag/8180 + |
| instance of | microprocessor + |
| ldate | 1900 + |