Edit Values
Mongoose 3 µarch
General Info
Arch Type	CPU
Designer	Samsung
Manufacturer	Samsung
Introduction	2018
Process	10 nm
Core Configs	4
Pipeline
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
Decode	6-way
Instructions
ISA	ARMv8
Cache
L1I Cache	64 KiB/core 4-way set associative
L1D Cache	32 KiB/core 8-way set associative
L2 Cache	2 MiB/cluster 16-way set associative
Succession
Mongoose 2 Mongoose 4

Mongoose 3 (M3) is an ARM microarchitecture designed by Samsung for their consumer electronics serving as a successor to the Mongoose 2.

Process Technology

The M3 was fabricated on Samsung's second generation 10LPP (Low Power Plus) process.

Compiler support

Compiler	Arch-Specific	Arch-Favorable
GCC	-march=armv8-a+crypto	-mtune=exynos-m3

Architecture

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Key changes from Mongoose 1/M2

• 10nm 10LPP process (from 1st gen 10LPP)
• Core
  • Front-end
    • larger instruction queue (40 entries, up from 24)
    • 6-way decode (from 4)
    • µOP fusion
      • Can fuse address generation and memory operations
      • Can fuse literal generation operations
  • Back-end
    • larger ReOrder buffer (228 entries, from 96 entries)
    • Has a fastpath logical shift of up to 3 places
• branch misprediction penalty increased (16, from 14)

This list is incomplete; you can help by expanding it.

References

• LLVM: lib/Target/AArch64/AArch64SchedExynosM3.td