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Xeon Phi 7285
General Info
Designer	Intel
Manufacturer	Intel
Model Number	7285
Part Number	HJ8068303823800
S-Spec	SR3VE
Market	Workstation, Server, Supercomputer
Introduction	December 18, 2017 (announced) December 18, 2017 (launched)
Shop	Amazon
General Specs
Family	Xeon Phi
Series	x205
Locked	Yes
Frequency	1,300 MHz
Turbo Frequency	1,400 MHz (1 core)
Clock multiplier	15
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Knights Mill
Core Stepping	A0
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	68
Threads	272
Max Memory	384 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	0.55 V-1.2 V
TDP	250 W
Tcase	5 °C – 72 °C
TDTS	5 °C – 84 °C
Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647

Xeon Phi 7285 is a 68-core x86 many-core microprocessor introduced by Intel in late 2017 specifically designed to accelerate artificial intelligence workloads. This processor, which is fabricated on their own 14 nm process based on the Knights Mill microarchitecture, operates at a frequency of 1.3 GHz with a TDP of 250 W and a turbo of 1.4 GHz.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Knights Mill § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 4.25 MiB 4,352 KiB 4,456,448 B L1I$ 2.125 MiB 2,176 KiB 2,228,224 B 68x32 KiB 8-way set associative   L1D$ 2.125 MiB 2,176 KiB 2,228,224 B 68x32 KiB 8-way set associative   L2$ 34 MiB 34,816 KiB 35,651,584 B 0.0332 GiB     34x1 MiB 16-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2400 Supports ECC Yes Max Mem 384 GiB Controllers 2 Channels 6 Max Bandwidth 107.3 GiB/s 109,875.2 MiB/s 115.212 GB/s 115,212.498 MB/s 0.105 TiB/s 0.115 TB/s Bandwidth Single 17.88 GiB/s Double 35.76 GiB/s Quad 71.53 GiB/s Hexa 107.3 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 36 Configuration: x16, x8, x4, x2, x1

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 AVX-512 Advanced Vector 512-bit AVX512F AVX-512 Foundation AVX512CD AVX-512 Conflict Detection AVX512ER AVX-512 Exponential and Reciprocal AVX512PF AVX-512 Prefetch AVX512_4FMAPS AVX-512 Fused Multiply-Accumulate Packed Single Precision AVX512_4VNNIW AVX-512 Vector Neural Network Instructions Word Variable Precision AVX512_VPOPCNTDQ AVX-512 Vector Population Count Doubleword and Quadword ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT)