RISC-V
Instruction Set Architecture

General

• History
• Families

Base Variants(base)

• RV32
• RV64
• RV128

Standard Extensions(all)

• A
• B
• C
• D
• E
• F
• G
• I
• J
• L
• M
• N
• P
• Q
• T
• V

Topics

• Foundation
• Non-Standard Extensions
• Addressing Modes
• Registers
• Assembly
• Interrupts
• Microarchitectures

RISC-V has standardized a series of standard extensions beyond the integer base instructions which can be implemented or omitted as desired depending on the design goals (e.g. energy/area/performance/storage goals).

Overview

By default, only the core ISA must be implemented presenting great opportunity for area and energy optimization. However, additional functionality is sometimes desired. RISC-V comes with a series of standard extensions that enable additional functionality beyond the core ISA such as floating point and operations and bit manipulation. Extensions can be implemented and omitted as desired. Those extensions are:

• A - Atomic instructions
• B - Bit manipulation instructions
• C - Compressed instructions
• D - Double-precision floating-point instructions
• E - Embedded applications, resource-constrained subset
• F - Single-precision floating-point instructions
• G - General (I + M + A + F + D)
• I - Integer base instructions
• J - Dynamically translated languages
• L - Decimal floating point instructions
• M - Integer multiplication and division instructions
• N - User-level interrupt instructions
• P - Packed-SIMD instructions
• Q - Quad-precision floating-point instructions
• T - Transactional Memory instructions
• V - Vector operations instructions

Naming Convention

RISC-V defines an exact order that must be used to define the RISC-V ISA subset:

RV [32, 64, 128] I, M, A, F, D, G, Q, L, C, B, J, T, P, V, N

For example, RV32IMAFDQC is legal, whereas RV32IMAFDCQ is not.