From WikiChip
Core i3-9100T - Intel
Edit Values | |
Core i3-9100T | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | i3-9100T |
Market | Desktop |
Shop | Amazon |
General Specs | |
Family | Core i3 |
Series | i3-9000 |
Locked | Yes |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Ice Lake |
Core Name | Ice Lake S |
Process | 10 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 4 |
Threads | 8 |
Max Memory | 64 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 35 W |
Core i3-9100T is a planned 64-bit mid-range performance x86 desktop processor by Intel set to be introduced in 2018/2019. The i3-9100T is fabricated on Intel's 2nd generation 10nm+ process based on the Ice Lake microarchitecture.
Cache
- Main article: Ice Lake § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
Facts about "Core i3-9100T - Intel"
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |