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Xeon Gold 6136 - Intel
Edit Values | |
Xeon Gold 6136 | |
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General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6136 |
Part Number | CD8067303405800 |
S-Spec | SR3B2 QMRX (QS) |
Market | Server |
Introduction | April 25, 2017 (announced) July 11, 2017 (launched) |
Release Price | $2460.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6000 |
Locked | Yes |
Frequency | 3,000 MHz |
Turbo Frequency | 3,700 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 30 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | H0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 12 |
Threads | 24 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Electrical | |
TDP | 150 W |
Tcase | 0 °C – 85 °C |
TDTS | 0 °C – 103 °C |
Packaging | |
Template:packages/intel/fclga-3647 |
Xeon Gold 6136 is a 64-bit dodeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6136, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3 GHz with a TDP of 150 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Cache
- Main article: Skylake § Cache
The Xeon Gold 6136 features a considerably larger non-default 24.75 MiB of L3, a size that would normally be found on an 18-core part.
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Frequencies
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | ||
Normal | 3,000 MHz | 3,700 MHz | 3,700 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz |
AVX2 | 2,600 MHz | 3,600 MHz | 3,600 MHz | 3,400 MHz | 3,400 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz |
AVX512 | 2,100 MHz | 3,500 MHz | 3,500 MHz | 3,300 MHz | 3,300 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz |
Benchmarks
Test: SPEC CPU2017
Tested: 2017-10-07 20:52:23-0400
Chips: 2, Cores: 24, Copies: 48
Vendor: HPE
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
Tested: 2017-10-07 20:52:23-0400
Chips: 2, Cores: 24, Copies: 48
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
SPECrate2017_fp_base: 159
Test: SPEC CPU2017
Tested: 2017-10-13 04:45:58-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: HPE
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
Tested: 2017-10-13 04:45:58-0400
Chips: 2, Cores: 24, Threads: 24
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
SPECspeed2017_fp_base: 103
Test: SPEC CPU2017
Tested: 2017-10-13 05:57:20-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: HPE
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
Tested: 2017-10-13 05:57:20-0400
Chips: 2, Cores: 24, Threads: 24
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
SPECspeed2017_int_base: 8.8
Test: SPEC CPU2017
Tested: 2017-10-07 16:38:18-0400
Chips: 2, Cores: 24, Copies: 48
Vendor: HPE
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
Tested: 2017-10-07 16:38:18-0400
Chips: 2, Cores: 24, Copies: 48
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
SPECrate2017_int_base: 149
Facts about "Xeon Gold 6136 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6136 - Intel#io +, Xeon Gold 6136 - Intel +, Xeon Gold 6136 - Intel +, Xeon Gold 6136 - Intel + and Xeon Gold 6136 - Intel + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
supported memory type | DDR4-2666 + |