From WikiChip
QorIQ P1021 - Freescale
Edit Values | |||||||
QorIQ P1021 | |||||||
![]() | |||||||
General Info | |||||||
Designer | Freescale | ||||||
Manufacturer | IBM | ||||||
Model Number | P1021 | ||||||
Market | Networking, Embedded | ||||||
Introduction | December 7, 2009 (announced) January, 2010 (launched) | ||||||
General Specs | |||||||
Family | QorIQ | ||||||
Series | P1 | ||||||
Frequency | 1,200 | ||||||
Microarchitecture | |||||||
ISA | Power ISA v2.03 (Power) | ||||||
Microarchitecture | e500 | ||||||
Core Name | e500 v2 | ||||||
Process | 45 nm | ||||||
Technology | CMOS | ||||||
Word Size | 32 bit | ||||||
Cores | 2 | ||||||
Threads | 2 | ||||||
Electrical | |||||||
Power dissipation | 4.5 W | ||||||
Packaging | |||||||
|
QorIQ P1012 is a 32-bit dual-core embedded POWER microprocessor introduced by Freescale in late 2009. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 1,200 MHz and supports 32-bit DDR3-800 memory.
Cache
- Main article: e500 § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||
|
Memory controller
![]() |
Integrated Memory Controller
|
|||||||||||||
|
Expansions
- 3x 10/100/1000 Eithernet with 2x SGMII
- 2x PCIe 1.0a controllers with 4 SerDes
- 2x USB 2.0
- SD/MMC
- SPI
- 2x I2C
- UART
- SEC 3.3 Security Acceleration
Block Diagram
Documents
Facts about "QorIQ P1021 - Freescale"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | QorIQ P1021 - Freescale#package + |
base frequency | 1,200 MHz (1.2 GHz, 1,200,000 kHz) + |
core count | 2 + |
core name | e500 v2 + |
designer | Freescale + |
family | QorIQ + |
first announced | December 7, 2009 + |
first launched | January 2010 + |
full page name | freescale/qoriq/p1021 + |
has ecc memory support | true + |
instance of | microprocessor + |
isa | Power ISA v2.03 + |
isa family | Power + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
ldate | January 2010 + |
main image | ![]() |
manufacturer | IBM + |
market segment | Networking + and Embedded + |
max memory bandwidth | 2.98 GiB/s (3,051.52 MiB/s, 3.2 GB/s, 3,199.751 MB/s, 0.00291 TiB/s, 0.0032 TB/s) + |
max memory channels | 1 + |
microarchitecture | e500 + |
model number | P1021 + |
name | QorIQ P1021 + |
package | TE-PBGA-II-689 + |
power dissipation | 4.5 W (4,500 mW, 0.00603 hp, 0.0045 kW) + |
process | 45 nm (0.045 μm, 4.5e-5 mm) + |
series | P1 + |
supported memory type | DDR3-800 + |
technology | CMOS + |
thread count | 2 + |
word size | 32 bit (4 octets, 8 nibbles) + |