Semiconductor & Computer Engineering
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QorIQ P1010 - Freescale
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| QorIQ P1010 | |||||||||
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| General Info | |||||||||
| Designer | Freescale | ||||||||
| Manufacturer | IBM | ||||||||
| Model Number | P1010 | ||||||||
| Market | Networking, Embedded | ||||||||
| Introduction | June 16, 2008 (announced) 2009 (launched) | ||||||||
| General Specs | |||||||||
| Family | QorIQ | ||||||||
| Series | P1 | ||||||||
| Frequency | 667 MHz, 800 MHz | ||||||||
| Microarchitecture | |||||||||
| ISA | Power ISA v2.03 (Power) | ||||||||
| Microarchitecture | e500 | ||||||||
| Core Name | e500 v2 | ||||||||
| Process | 45 nm | ||||||||
| Technology | CMOS | ||||||||
| Word Size | 32 bit | ||||||||
| Cores | 1 | ||||||||
| Threads | 1 | ||||||||
| Electrical | |||||||||
| Power dissipation | 1.6 W | ||||||||
| Tjunction | 0 °C – 125 °C | ||||||||
| Packaging | |||||||||
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QorIQ P1010 is a 32-bit embedded POWER microprocessor introduced by Freescale in 2008. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 667 MHz and supports 32-bit DDR3-800 memory.
Cache
- Main article: e500 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
- 2x 10/100/1000 Eithernet with SGMII
- 2x PCIe 1.0a controllers with 2 SerDes
- 2x USB 2.0
- SD/MMC
- SPI
- 2x I2C
- UART
- SEC 3.1 Security Acceleration
Block Diagram
Documents
Facts about "QorIQ P1010 - Freescale"
| has ecc memory support | true + |
| l1$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| max memory bandwidth | 2.98 GiB/s (3,051.52 MiB/s, 3.2 GB/s, 3,199.751 MB/s, 0.00291 TiB/s, 0.0032 TB/s) + |
| max memory channels | 1 + |
| supported memory type | DDR3-800 + |