Template:mpu K3V2 is a 32-bit quad-core mobile ARM microprocessor introduced by HiSilicon in early 2012. This chip, which is fabricated on a 40 nm process, incorporates four Cortex-A9 cores operating at 1.2 GHz. The K3V2 integrated Vivante's GC4000 (16 cores) IGP and supports up to 2 channels of LPDDR2-900 memory.

Cache

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 4-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 4-way set associative   L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     1x1 MiB 8-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR2-900 Supports ECC No Controllers 1 Channels 2 Width 32 bit Max Bandwidth 6.71 GiB/s 6,871.04 MiB/s 7.205 GB/s 7,204.808 MB/s 0.00655 TiB/s 0.0072 TB/s Bandwidth Single 3.35 GiB/s Double 6.71 GiB/s