From WikiChip
K3V1 - HiSilicon
Edit Values | |||||||||
K3V1 | |||||||||
General Info | |||||||||
Designer | HiSilicon, ARM Holdings | ||||||||
Manufacturer | TSMC | ||||||||
Model Number | K3V1 | ||||||||
Part Number | Hi3611 | ||||||||
Market | Mobile | ||||||||
Introduction | June, 2008 (announced) June, 2008 (launched) | ||||||||
General Specs | |||||||||
Family | K3 | ||||||||
Frequency | 460 | ||||||||
Microarchitecture | |||||||||
ISA | ARMv5 (ARM) | ||||||||
Microarchitecture | ARM9 | ||||||||
Core Name | ARM926EJ-S | ||||||||
Process | 0.18 µm | ||||||||
Transistors | 200,000,000 | ||||||||
Technology | CMOS | ||||||||
Word Size | 32 bit | ||||||||
Cores | 1 | ||||||||
Threads | 1 | ||||||||
Multiprocessing | |||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||
Electrical | |||||||||
VI/O | 1.8 V, 2.5 V | ||||||||
Packaging | |||||||||
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K3V1 is a 32-bit performance ARM microprocessor introduced by HiSilicon in 2008. This chip incorporates a single ARM9 core with Jazelle support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.
Contents
Cache
- Main article: ARM9 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
- 4x high-speed UART interfaces
- 2x SPI
- 2x I2C
- USB 2.0 On-The-Go (HS OTG) PHY
- USB 1.1
- 2x MMC/SD/SDIO interface
- 14x GPIOs
- 8 Timers
Features
[Edit/Modify Supported Features]
Supported ARM Extensions & Processor Features
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Graphics
The K3V1 integrated graphics engine, although the exact specs are not available.
- Support QVGA, WQVGA, VGA display resolutions
- Hardware-acceleration video
- 200 KiB Frame Buffer
Camera
- Support 30 million pixel camera, up to 30fps
- Supports up to 8 megapixel CMOS Sensor image input
Audio
- Built-in high-performance audio CODEC
- Sampling frequency support 44.1kHz and 48kHz
- support for sound playback and recording
- High quality stereo playback DAC and 1 channel Voice DAC, 2 channels
- ADC, CODEC support any audio mixing, independent of the amplifier Output gain control
Block Diagram
Documents
Facts about "K3V1 - HiSilicon"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | K3V1 - HiSilicon#package + |
base frequency | 460 MHz (0.46 GHz, 460,000 kHz) + |
core count | 1 + |
core name | ARM926EJ-S + |
designer | HiSilicon + and ARM Holdings + |
family | K3 + |
first announced | June 2008 + |
first launched | June 2008 + |
full page name | hisilicon/k3/k3v1 + |
has ecc memory support | false + |
instance of | microprocessor + |
io voltage | 1.8 V (18 dV, 180 cV, 1,800 mV) + and 2.5 V (25 dV, 250 cV, 2,500 mV) + |
isa | ARMv5 + |
isa family | ARM + |
l1$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
ldate | June 2008 + |
manufacturer | TSMC + |
market segment | Mobile + |
max cpu count | 1 + |
max memory channels | 1 + |
microarchitecture | ARM9 + |
model number | K3V1 + |
name | K3V1 + |
package | TFBGA-460 + |
part number | Hi3611 + |
process | 180 nm (0.18 μm, 1.8e-4 mm) + |
smp max ways | 1 + |
supported memory type | DDR + |
technology | CMOS + |
thread count | 1 + |
transistor count | 200,000,000 + |
word size | 32 bit (4 octets, 8 nibbles) + |