Template:mpu W-2175 is a 64-bit 14-core x86 enterprise performance workstation microprocessor introduced by Intel in 2017. This processors, which is fabricated on an enhanced 14nm+ process based on the Skylake server microarchitecture, operates at ? GHz with a TDP of 140 W and a turbo boost frequency of up to ? GHz. This chip supports up to 512 GiB of quad-channel DDR4-2666 ECC memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 896 KiB 917,504 B 0.875 MiB L1I$ 448 KiB 458,752 B 0.438 MiB 14x32 KiB 8-way set associative   L1D$ 448 KiB 458,752 B 0.438 MiB 14x32 KiB 8-way set associative write-back L2$ 14 MiB 14,336 KiB 14,680,064 B 0.0137 GiB     14x1 MiB 16-way set associative write-back L3$ 19.25 MiB 19,712 KiB 20,185,088 B 0.0188 GiB     14x1.375 MiB 11-way set associative write-back

Memory controller

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	Integrated Memory Controller
	Max Type DDR4-2666 Supports ECC Yes Max Mem 512 GiB Controllers 2 Channels 4 Max Bandwidth 79.47 GiB/s 81,377.28 MiB/s 85.33 GB/s 85,330.263 MB/s 0.0776 TiB/s 0.0853 TB/s Bandwidth Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s Physical Address (PAE) 46 bit

Expansions

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	Expansion Options
PCIe Revision: 3.0 Max Lanes: 48 Configuration: x16, x8, x4