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z14 µarch
General Info
Arch Type	CPU
Designer	IBM
Manufacturer	GlobalFoundries
Introduction	July 17, 2017
Process	14 nm
Pipeline
Type	Superscalar, Pipelined
Instructions
ISA	z/Architecture
Succession
z12

z14 was a z/Architecture-based microarchitecture designed by IBM and introduced in 2017 for their z14 processors and mainframes. The z14 microarchitecture replaced the z13.

Process Technology

z14-based microprocessors are manufactured on GlobalFoundries's 14 nm FinFET Silicon-On-Insulator (SOI).

Architecture

Key changes from z13

• 14 nm process (from 22 nm)
• Higher clock frequency (5.2 GHz from 5 GHz)
• Higher scalability
  • Up to 170-way multiprocessing (from 141-way)
• Core
  • Improved Operand Store Compare (OSC) prediction
  • Faster branch wakeup
  • Improved instruction delivery
• Cache
  • New directory design
    • Power efficient
  • L1I$ increased to 128 KiB/core (from 96 KiB/core; 33% increase)
  • L2D$ increased to 4 MiB/core (from 2 MiB/core; 100% increase)
  • L3$ increased to 128 MiB/CP (from 64 MiB/CP; 100% increase)
  • New 672 MiB/drawer of shared L4

• Central Processor Assist for Cryptographic Function (CPACF)
  • Dedicated co-processor for each core
  • Claims 6x faster encryption functions (vs. z13)
    • 4x Advanced Encryption Standard (AES) speedup
  • Support for True Random Number Generator
  • New support for SHA-3 standard

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Overview

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Die

Core

Below is a layout of a single physical core

Single-chip module (SCM)

IBM's z14 Single-Chip Module (SCM) consists of a multi-layer metal substrate module that includes either:

• 1x Processor Unit (PU)
• 1x System Controller (SC)

Processor Unit (PU) Chip

• IBM's developed (now GlobalFoundries) 14HP Process
  • CMOS FinFET SOI
  • 17 Metal Layers
• 25.3 x 27.5 mm die
• 695.75 mm² die size
• deca-core
• 5.2 GHz (192 ps cycle time)

System Controller (SC) Chip

• IBM's developed (now GlobalFoundries) 14HP Process
  • CMOS FinFET SOI
  • 17 Metal Layers
• 25.3 x 27.5 mm die
• 695.75 mm² die size
• 7,100,000,000 transistors
• + 2,100,000,000 cells of eDRAM (~2.1B xTors + 2.1B capacitors)
  • 672 MiB shared eDRAM L4 Cache